• Title/Summary/Keyword: Electronic Power Consumption

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Double Opportunistic Transmit Cooperative Relaying System with GSC in Rayleigh Fading Channels

  • Kim, Nam-Soo;Lee, Ye-Hoon
    • Journal of electromagnetic engineering and science
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    • v.10 no.4
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    • pp.270-275
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    • 2010
  • In a conventional opportunistic transmit (COT) cooperative relaying system, only the relays that receive signal-to-noise ratio (SNR) from the source and that exceed the threshold transmit to the destination. The COT system, however, only considers the SNR of the source-relay (S-R) path regardless that the SNR of the relay-destination (R-D) path is the opportunistic transmission condition. For that reason, it is not guaranteed that all the transmitted signals from relays exceed the threshold at the destination. Therefore we propose a double opportunistic transmit (DOT) cooperative relaying system - when both of the received SNR from a source and from a destination exceed the threshold, the relay transmits to the destination. It is shown that the proposed DOT system reduces power consumption by 6.9, 20.9, 32.4, and 41.4 % for K =3, 5, 7, and 9, respectively under the given condition of $P_{out}=1{\times}10^{-3}$ and $\overline{\gamma}_{SR}/\Gamma_{SR}$=30 dB, compared to the COT system. We noticed that the performance of the DOT system is superior to that of the COT system for the identical number of active transmit relays under the same condition of the normalized average SNR of $\overline{\gamma}_{RD}/\Gamma_{RD}$.

Low Temperature Fluidity Test System of Composited Package Fuel Heater for Diesel Cars (디젤차량용 통합연료히터의 저온유동성 시험장치개발)

  • Jang, Young-Sung;Yoon, Dal-Hwan
    • Journal of IKEEE
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    • v.18 no.2
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    • pp.185-191
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    • 2014
  • In this paper, we have implemented the low temperature fluidity test system with the composited package fuel heater, which has tested the low temperature fluidity and start time to evaluate the performance. Then we have compared the separation and the unified fuel heater type at $+20{\sim}-30^{\circ}C$. Also, we have tested the flowing pressure and start time, power consumption of heater. By comparing the performance with several condition, the experimental results obtain an improved start time of 23% and low temperature fluidity of 19%.

A Study on Light Quality of LED for Control of Light Intensity (광 강도 제어에 따른 LED의 광질에 관한 연구)

  • Park, Sang-Hee;An, Jun-Chul;Heo, Jung-Wook;Choi, Han-Ko;Choi, Sung-Dae
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.11 no.6
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    • pp.175-182
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    • 2012
  • Light characteristics of the monochromatic red(R), blue(B), green(G) and white(W) and the mixed LED (B-R LED) were investigated by light control a Spectrometer-MMS1 and an illuminometer. The power consumption of each LED was 1W and R LED has five wavelength bands(600nm, 640nm, 660nm, 680nm, 750nm). The light intensity of each LED was changed in a range 10~100%. As a results, the wavelength and the spectrum distribution of R LED increase with increasing light intensity but the wavelength of B, G, W LED decreases. It was found that illumination of each mononochromatic and B-R LED increases linearly with increasing light intensity. It was confirmed that the illumination intensity of R-B light has greater values than those obtained by monochromatic light at the same conditions.

A Study of an 8-b${\times}$8-b Adiabatic Pipelined Multiplier with Simplified Supply Clock Generator (단열회로를 이용한 8-b${\times}$8-b 파이프라인 승산기와 개선된 전원클럭 발생기의 연구)

  • Moon, Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.4
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    • pp.285-291
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    • 2001
  • An 8-b$\times$8-b adiabatic pipelined multiplier is designed. Simplified four phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and are integrated using 0.6${\mu}{\textrm}{m}$ CMOS technology. The efficiency of proposed supply clock generator is better than the previous one by 4~11%. Simulation results show that the power consumption of adiabatic pipelined multiplier is reduced by a factor of 2.6~3.5 compared to a conventional pipelined CMOS multiplier.

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Random Pixel Sampling-based Backlight Dimming for Liquid Crystal Display (LCD 디스플레이를 위한 무작위 화소 추출 기반 백라이트 디밍)

  • Kang, Suk-Ju;Kim, Young Hwan
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.11
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    • pp.174-180
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    • 2014
  • In this paper, we propose the random pixel sampling technique to solve the high computational complexity in the perceptual SSIM-based backlight dimming. Specifically, the proposed algorithm selects pixels in a total frame considering the pre-defined number, and generates the block by combining these pixels. Then, it estimates parameters, which are required in the SSIM calculation, in the combined block, and hence, it can reduce the computation time significantly. In the experimental results, the proposed algorithm reduced the average power consumption and computation time by up to 38.1776 % and 99.5828 %, respectively while preserving the average SSIM., compared with the conventional algorithm.

Efficient Design of BCD-EXCESS 3 Code Converter Using Quantum-Dot Cellular Automata (QCA를 이용한 효율적인 BCD-3초과 코드 변환기 설계)

  • You, Young-Won;Jeon, Jun-Cheol
    • Journal of Advanced Navigation Technology
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    • v.17 no.6
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    • pp.700-704
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    • 2013
  • Quantum-dot cellular automata(QCA) is a new technology and it is an one of the alternative high performance over existing complementary metal-oxide semi-conductor(CMOS). QCA is nanoscale device and ultra-low power consumption compared with transistor-based technologies, and various circuits using QCA technology have been proposed. Binary-coded decimal(BCD), which represents decimal digits in binary, is mainly used in electronic circuits and Microprocessor, and it is comfortable in conversion operation but many data loss. In this paper, we present an BCD-EXCESS 3 Code converter which can be efficiently used for subtraction and half adjust. The proposed scheme has efficiently designed considering space and time complexities and minimization of noise, and it has been simulated and confirmed.

The Glass Greenhouse's Lighting Simulation for Ginseng with Solar Cell and LED (태양전지와 LED를 이용한 인삼재배용 유리온실의 조도 시뮬레이션)

  • Lee, Boong-Joo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.20 no.2
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    • pp.14-19
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    • 2019
  • In this study, the Relux illumination program was used to simulate the optimal lighting design for a glass greenhouse with Si and DSSC solar-cells and LEDs. The results of the daylight simulation show that the optimum conditions were a structure angle of 90o and higher transmittance. The results of the illumination simulation produced a power consumption effect of 5.6 kwh in the summer (42[%] energy savings compared to full LED control) and 7.8 kwh in the winter (58[%] energy savings compared to full LED control). The results suggest that ginseng should be grown in an energy-saving glass greenhouse.

Analysis of influence of fuel consumption on change of electric energy of internal combustion engine (내연기관 차량의 전기에너지 변화에 따른 연비 영향성 분석)

  • Ko, Da-Som;Kim, Tae-Hoon;Jeong, Jin-Beom
    • Proceedings of the KIPE Conference
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    • 2019.07a
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    • pp.471-472
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    • 2019
  • 자동차 산업은 친환경 규제 대응과 함께 운전자의 안전성, 편의성 등 운전자의 가치 증대에 초점을 맞추어 IT기술이 융합된 전장기술의 필요성이 증가하고 있으며, 기술 개발이 활발히 진행되고 있다. 이는 하이브리드 자동차나 전기자동차에 사용되는 인버터, 컨버터, 충전기 등의 전력변환장치뿐만 아니라 기존의 내연기관 자동차의 전자 샤시(electronic chassis), 지능형 자동차, 48V 전력시스템 등 다양한 부문의 전장품 개발을 포함한다. 전장품의 증가는 필수적으로 전력부하의 증가를 의미한다. 이러한 전기에너지 소모량 증가에 따른 대안으로 태양광 자동차 같은 친환경 에너지를 보조 전원으로 활용하는 자동차들이 개발되기도 한다. 하지만 이러한 차량 전기에너지의 감소 또는 증가가 연비에 미치는 영향을 판단할 수 있는 관련 연구를 찾기 어려울 뿐만 아니라 현장의 차량 설계자들은 실제 차량을 구현하기 전까지 전기 에너지 변화에 따른 연비 영향성을 판단하기 어려운 실정이다. 이에 따라, 본 논문에서는 내연 기관 차량의 전기에너지 변화에 따른 연비 영향성을 분석하여 보다 효율적인 에너지 사용 방안에 대해 고찰한다. 상용 시뮬레이션 프로그램을 이용하여 전기에너지 사용별 연비에 미치는 영향을 분석한다.

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SoC Implementation of Deblocking Filter for Block-based Compressed Images and Videos (블록 기반 압축 이미지 및 비디오를 위한 디블로킹 필터의 SoC 구현)

  • Seo, Gwang-Seok;Lee, Joo-Heung
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.925-933
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    • 2019
  • In this paper, we implement ZYNQ SoC-based post-processing system that utilizes partial reconfiguration to remove blocking artifacts generated by compression algorithm. Hardware implementation of the deblocking filter in a Field Programmable Gate Array (FPGA) provides high computational capability and can be partially reconfigured to process 1080p images in real time. Partially reconfigurable areas in FPGA can be utilized to use hardware more efficiently in highly resource-constrained embedded systems. Experimental results of the proposed system show improvement of visual quality both objectively and subjectively with 0.6dB higher PSNR after deblocking filtering process. The measured power consumption of the deblocking filter during run-time is 68.33mW.

Low cost 2.4-GHz VCO design in 0.18-㎛ Mixed-signal CMOS Process for WSN applications (저 가격 0.18-㎛ 혼성신호 CMOS공정에 기반한 WSN용 2.4-GHz 밴드 VCO설계)

  • Jhon, Heesauk;An, Chang-Ho;Jung, Youngho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.24 no.2
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    • pp.325-328
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    • 2020
  • This paper demonstrated a voltage-controlled oscillator (VCO) using cost-effective (1-poly 6-metal) mixed signal standard CMOS process. To have the high-quality factor inductor in LC resonator with thin metal thickness, patterned-ground shields (PGS) was adopted under the spiral to effectively reduce the ac current of low resistive Si substrate. And, because of thin top-metal compared with that of RF option (2 ㎛), we make electrically connect between the top metal (M6) and the next metal (M5) by great number of via array along the metal traces. The circuit operated from 2.48 GHz to 2.62 GHz tuned by accumulation-mode varactor device. And the measured phase noise of LC VCO has -123.7 dBc/Hz at 1MHz offset at 2.62 GHz and the dc-power consumption shows 2.07 mW with 1.8V supply voltage, respectively.