Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Study of an 8-b${\times}$8-b Adiabatic Pipelined Multiplier with Simplified Supply Clock Generator

단열회로를 이용한 8-b${\times}$8-b 파이프라인 승산기와 개선된 전원클럭 발생기의 연구

  • Moon, Yong (School of Electronic Engineering, Soongsil University)
  • 문용 (숭실대학교 정보통신전자공학부)
  • Published : 2001.04.01
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Abstract

An 8-b$\times$8-b adiabatic pipelined multiplier is designed. Simplified four phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and are integrated using 0.6${\mu}{\textrm}{m}$ CMOS technology. The efficiency of proposed supply clock generator is better than the previous one by 4~11%. Simulation results show that the power consumption of adiabatic pipelined multiplier is reduced by a factor of 2.6~3.5 compared to a conventional pipelined CMOS multiplier.

단열회로를 이용한 8-b×8-b 파이프라인 승산기와 4가지 위상을 가지는 전원클럭을 공급하기 위한 개선 된 구조의 전원클럭 발생기를 설계하였다. 전원클럭 신호선의 전하는 복원되어 에너지 소모를 줄인다. 단열회로는 ECRL 형태를 기본으로 하였으며 0.6㎛ CMOS 공정을 사용하여 설계하였다. 개선된 전원클럭 발생기는 기존회로보다 4∼11% 정도 효율이 높았다. 모의실험결과 제안하는 단열회로 승산기는 CMOS 승산기보다 2.6∼3.5배 정도의 에너지를 감소시켰다.

Keywords

References

  1. J. S. Denker, 'A review of adiabatic computing,' IEEE Symposium on Low Power Electronics, Digest of Technical Papers, pp. 94-97, 1994 https://doi.org/10.1109/LPE.1994.573218
  2. A. Kramer, J. S. Denker, S. C. Avery, A. G. Dickinson and T. R. Wik, 'Adiabatic computing with the 2N-2N2D logic family,' in Symp. on VLSI Circuits Dig. of Tech Papers, pp. 25-26, 1994
  3. R. T. Hinman and M. F. Schlecht, 'Power dissipation measurements on recovered energy logic,' in Symp. on VLSI Circuits Dig. of Tech. Papers, pp. 19-20, 1994
  4. A. G. Dickinson and J. S. Denker, 'Adiabatic Dynamic Logic,' IEEE JSSC, vol. 30, pp. 311-315, March 1995 https://doi.org/10.1109/4.364447
  5. Y. Moon and D. K. Jeong, 'A 32$\times$32-b Adiabatic Register File with Supply Clock Generator,' IEEE JSSC, vol. 33, no. 5, pp. 696-701, May 1998 https://doi.org/10.1109/4.668983
  6. D. Suvakovic and C. Salama, 'Two Phase Non-Overlapping Clock Adiabatic Differential Cascode Voltage Switch Logic(ADCVSL),' IEEE ISSCC, Digest of Technical Papers, Vol. 43, pp. 364-365, 2000 https://doi.org/10.1109/ISSCC.2000.839817
  7. D. Maksimovic, V. G. Oklobdzija, B. Nikolic and K. W. Current, 'Clocked CMOS adiabatic logic with integrated single-phase power-clock supply,' IEEE Transactions on VLSI systems, Vol. 8, pp. 460-463, Aug. 2000 https://doi.org/10.1109/92.863629
  8. M. Hatamian and G. L. Cash, 'A 70-MHz 8-bit$\times$8-bit Parallel Pipelined Multiplier in $2.5-{\mu}m$ CMOS,' IEEE JSSC, vol. 21, No. 4, pp. 505-513, Aug. 1986
  9. J. Wang, P. Yang and D. Sheng, 'Design of a 3-V 300MHz Low-Power 8-b$\times$8-b Pipelined Multiplier Using Pulse-Triggered TSPC Flip-Flops,' IEEE JSSC, vol. 35, No. 4, pp. 583-592, April 2000 https://doi.org/10.1109/4.839918
  10. L. G. Heller and W. R. Griffin, 'Cascode Voltage Switch Logic: A Differential CMOS Logic Family,' ISSCC digest of Technical Papers, pp. 16-17, 1984
  11. K. M. Chu and D. I. Pulfrey, 'Design Procedures for Differential Cascode Voltage Switch Circuits,' IEEE JSSC, vol. 21, No. 6, pp. 1082-1087, Dec. 1986