• Title/Summary/Keyword: Electronic Power Consumption

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WBAN Service Quality Optimization Design Using Error Correction Technique (에러교정기법을 이용한 WBAN 서비스품질 최적화 설계)

  • Lee, Jung-Jae
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.4
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    • pp.657-662
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    • 2019
  • The power consumption of wearable sensors and electrocardiogram regulators should be very low to extend the network lifetime and anticipated QoS( : Quality of Service) control such as error correction and authentication of data processed by WBAN( : Wireless Body Area Network) nodes is important. Therefore, QoS control is the most urgent concern to implement WBAN in health monitoring regulations. For optimal QoS control, we compare the energy efficiency and the average number of transmissions with IEEE 802.15.6 and the error correction method considering energy efficiency. The performance of the proposed error correction technique shows that the energy efficiency and the transmission rate are improved by adjusting the coding rate appropriately using the channel estimation.

A Low Noise Phase Locked Loop with Three Negative Feedback Loops (세 개의 부궤환 루프를 가진 저잡음 위상고정루프)

  • Young-Shig Choi
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.16 no.4
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    • pp.167-172
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    • 2023
  • A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

Test Method of Communication Reliability based on HPGP between PEV and EVSE (전기차와 충전기 간 HPGP 기반 통신 신뢰성 테스트 방안)

  • Choi, Byeong-Gon;Kim, Kyung-Seok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.15 no.2
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    • pp.111-119
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    • 2015
  • Smart Grid is a next-generation intelligent grid to optimize energy efficiency by integrating information and communication technologies to the existing power grid as a two-way exchange of information. HPGP communication standard for smart grid implementation has been developed for the emerging smart energy, home automation, electric vehicle communications applications. HPGP communication standard has the advantage of reducing cost and power consumption. Also, it can be interoperated with the previous HPAV communication standard. For the introduction of a new communication standard, the analysis of the reliability and interoperability verification is required. In this paper, we present sniffer test method as reliability test method about power line communication between PEV(Plug-in Electric Vehicle) and EVSE(Electric Vehicle Supply Equipment). Power line communication between PEV and EVSE is one of the most important Smart Gird applications. Also, we analyzed sniffer test results about power line communication based on HPGP between PEV and EVSE by using QCA7000 device, AVitar and Tool kit.

Distributed Transmit Power Control Algorithm Based on Flocking Model for Energy-Efficient Cellular Networks (에너지 효율적인 셀룰러 네트워크를 위한 플로킹 모델 기반 분산 송신전력제어 알고리즘)

  • Choi, Hyun-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.10
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    • pp.1873-1880
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    • 2016
  • Most of the energy used to operate a cellular network is consumed by a base station (BS), and reducing the transmission power of a BS is required for energy-efficient cellular networks. In this paper, a distributed transmit power control (TPC) algorithm is proposed based on the flocking model to improve the energy efficiency of a cellular network. Just as each bird in a flock attempts to match its velocity with the average velocity of adjacent birds, in the proposed algorithm each mobile station (MS) in a cell matches its rate with the average rate of the co-channel MSs in adjacent cells by controlling the transmit power of its serving BS. Simulation results show that the proposed TPC algorithm follows the same convergence properties as the flocking model and also effectively reduces the power consumption at the BSs while maintaining a low outage probability as the inter-cell interference increases. Consequently, it significantly improves the energy efficiency of a cellular network.

A Mismatch-Insensitive 12b 60MS/s 0.18um CMOS Flash-SAR ADC (소자 부정합에 덜 민감한 12비트 60MS/s 0.18um CMOS Flash-SAR ADC)

  • Byun, Jae-Hyeok;Kim, Won-Kang;Park, Jun-Sang;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.7
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    • pp.17-26
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    • 2016
  • This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

Image Contrast Enhancement Technique for Local Dimming Backlight of Small-sized Mobile Display (소형 모바일 디스플레이의 Local Dimming 백라이트를 위한 영상 컨트라스트 향상 기법)

  • Chung, Jin-Young;Yun, Ki-Bang;Kim, Ki-Doo
    • 전자공학회논문지 IE
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    • v.46 no.4
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    • pp.57-65
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    • 2009
  • This paper presents the image contrast enhancement technique suitable for local dimming backlight of small-sized mobile display while achieving the reduction of the power consumption. In addition to the large-sized TFT-LCD, small-sized one has adopted LED for backlight. Since, conventionally, LED was mounted on the side edge of a display panel, global dimming method has been widely used. However, recently, new advanced method of local dimming by placing the LED to the backside of the display panel and it raised the necessity of sub-blocked processing after partitioning the target image. When the sub-blocked image has low brightness, the supply current of a backlight LED is reduced, which gives both enhancement of contrast ratio and power consumption reduction. In this paper, we propose simple and improved image enhancement algorithm suitable for the small-sized mobile display. After partitioning the input image by equal sized blocks and analyzing the pixel information in each block, we realize the primary contrast enhancement by independently processing the sub-blocks using the information such as histogram, mean, and standard deviation values of luminance(Y) component. And then resulting information is transferred to each backlight control unit for local dimming to realize the secondary contrast enhancement as well as reduction of power consumption.

A Study of Development and Product ion Technology for Camcoder Iris Assembly (캠코더용 Iris Assembly의 국산화 및 생산 기술 개발 사례)

  • Ko, Jong-Sun
    • Proceedings of the KIEE Conference
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    • 1996.07a
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    • pp.250-252
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    • 1996
  • In this paper, the principle of operation. the part characteristic, characteristic of component movement, analysis are carried out for camcoder iris assembly which is one of the important element component in Video large projection TV instrument, and some Know-how for development of element component is also included. The magnetic field circuit for the small and simple structure with low power consumption is introduced and new materials of yoke for small motor system is suggested. Especially, the relation with remained magnetic field and operation duration time is analyzed by experimental results. Some problems of nonlinear torque characteristics include to obtain the simple and low cost structure in domestic production of element component is analyzed. Furthermore, development procedure is suggested for iris assembly and some methods to reduce the burr with some check points for small precise accessories are explained.

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CMOS Direct-Conversion RF Front-End Design for 5-GHz WLAN

  • Oh, Nam-Jin
    • Journal of electromagnetic engineering and science
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    • v.8 no.3
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    • pp.114-118
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    • 2008
  • Direct-conversion RF front-end for 5-GHz WLAN is implemented in $0.18-{\mu}m$ CMOS technology. The front-end consists of a low noise amplifier, and low flicker noise down-conversion mixers. For the mixer, an inductor is included to resonate out parasitic tail capacitances in the transconductance stage at the operating frequency, thereby improves the flicker noise performance of the mixer, and the overall noise performance of the front-end. The receiver RF front-end has 6.5 dB noise figure, - 13 dBm input IP3, and voltage conversion gain of 20 dB with the power consumption of 30 mW.

A Quadrature VCO Exploiting Direct Back-Gate Second Harmonic Coupling

  • Oh, Nam-Jin
    • Journal of electromagnetic engineering and science
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    • v.8 no.3
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    • pp.134-137
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    • 2008
  • This paper proposes a novel quadrature VCO(QVCO) based on direct back-gate second harmonic coupling. The QVCO directly couples the current sources of the conventional LC VCOs through the back-gate instead of front-gate to generate quadrature signals. By the second harmonic injection locking, the two LC VCOs can generate quadrature signals without using on-chip transformer, or stability problem that is inherent in the direct front-gate second harmonic coupling. The proposed QVCO is implemented in $0.18{\mu}m$ CMOS technology operating at 2 GHz with 5.0 mA core current consumption from 1.8 V power supply. The measured phase noise of the proposed QVCO is - 63 dBc/Hz at 10 kHz offset, -95 dBc/Hz at 100 kHz offset, and -116 dBc/Hz at 1 MHz offset from the 2 GHz output frequency, respectively. The calculated figure of merit(FOM) is about -174 dBc/Hz at 1 MHz offset. The measured image band rejection is 46 dB which corresponds to the phase error of $0.6^{\circ}$.

The Illumination Simulation in the Greenhouse using Daylight and Artificial Light for Energy Saving. (에너지 절감을 위한 자연광과 인공광원을 활용한 유리온실 조도 시뮬레이션)

  • Lee, Boong-Joo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.9
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    • pp.1359-1363
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    • 2017
  • In this study, the Relux program was simulated for optimum conditions of daylight and artificial light sources(LED) in the glass greenhouse. From the results of daylight simulation, the optimum design conditions for the glass greenhouse were established which were 90[o] installation angle and higher transmittance. In this case of growing lettuce in the glass greenhouse, the control method of the only artificial light source was compared that of daylight and LED. The result of illumination simulation produced a power consumption effect of 37.2[%] in the summer and 51.9[%] in the winter, respectively. From this results, we propose to suggest that we grow the lettuce in the energy saving glass greenhouse.