• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.991-994
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• 2003

Electronic Paper용 무기소재로 $TiO_2$ 나노입자를 적용하기 위해서는 분산시 침전문제, 입자의 전기영동 속도향상을 위한 충분한 $\xi-potential$확보, 분산제 첨가시 안정적 결합을 위한 acidic site의 확보등의 문제가 해결되어야 한다. 이를 위해 저온균일침전법으로 $TiO_2$ 나노입자를 제조하였고, 폴리머 체인을 통하여 encapsulation하여 최적의 분산과 전기영동조건 확보를 위한 공정조건에 대해 연구하였다. 실험결과 다양한 분산매에 계면활성제를 1.0wt% 첨가시 유전율상수가 2.5인 분산매에서 가장 좋은 $\xi-potential$을 얻을 수 있었으며 이를 바탕으로 acidic site에 따른 폴리머 체인의 흡착실험 결과 pH $1{\sim}2$의 조건에서 제조된 $TiO_2$ 나노입자의 경우가 체인과의 흡착정도가 가장 좋아 분산특성을 향상시킬 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.835-837
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• 2012

In this paper, we have been analyzed conduction path by device parameter of double gate(DG) structure that have top gate and bottom gate. The Possion equation is used to analytical. The change of conduction path have been investigated for various channel lengths, channel thickness and gate oxide thickness using this model, given that these parameters are very important in design of DGMOSFET. The optimum channel doping concentration is determined as the deviation of conduction path is considered according to channel doping concentration.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.90-90
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• 2012

The electron/hole injections in organic electronic devices have long been an issue due to the large energy level mismatches between electrode and organic layer. To utilize the organic materials in electronic devices, functional thin layers have been used, which reduce the electron/hole injection barrier from electrode to organic material. Typically, inorganic compounds and organic molecules are used as an electron and hole injection layer, respectively. Recently, CsN3 and 1,4,5,8,- naphthalene-tetracarboxylic-dianhydride (NTCDA) are reported as a potential electron and hole injection layers. CsN3 shows unique properties that it breaks into Cs and N and thus Cs can dope organic layer into n-type. On the other side, hole injection anode, NTCDA forms gap states with anode material. In this presentation, we show the electronic structure changes upon the insertion of CsN3 and NTCDA at proper interfaces to reduce the charge injection barriers. These barrier reductions are correlated with device characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.11
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• pp.785-789
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• 2013

Silicon Carbide (SiC) is the material with the wide band-gap (3.26 eV), high critical electric field (~2.3 MV/cm), and high bulk electron mobility (~900 $cm^2/Vs$). These electronic properties allow attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. In general, device design has a significant effect on the switching and electrical characteristics. It is known that in this paper, we demonstrated that the switching performance and breakdown voltage of IGBT is dependent with doping concentration of p-base region and drift layer by using 2-D simulations. As a result, electrical characteristics of SiC-IGBT deivce is higher breakdown voltage ($V_B$= 1,600 V), lower on-resistance ($R_{on}$= 0.43 $m{\Omega}{\cdot}cm^2$) than Si-IGBT. Also, we determined that processing time and cost is reduced by the depth of n-drift region of IGBT was reduced.

• Transactions on Electrical and Electronic Materials
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• v.5 no.6
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• pp.227-232
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• 2004

We investigated a nonvolatile nanomemory element based on boron nitride nanopeapods using molecular dynamics simulations. The studied system was composed of two boron-nitride nanotubes filled Cu electrodes and fully ionized endo-fullerenes. The two boron-nitride nanotubes were placed face to face and the endo-fullerenes came and went between the two boron-nitride nanotubes under alternatively applied force fields. Since the endo-fullerenes encapsulated in the boron-nitride nanotubes hardly escape from the boron-nitride nanotubes, the studied system can be considered to be a nonvolatile memory device. The minimum potential energies of the memory element were found near the fullerenes attached copper electrodes and the activation energy barrier was $3{\cdot}579 eV$. Several switching processes were investigated for external force fields using molecular dynamics simulations. The bit flips were achieved from the external force field of above $3.579 eV/{\AA}$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.48-52
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• 2014

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

• Bulletin of the Korean Chemical Society
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• v.30 no.3
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• pp.647-652
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• 2009

A novel spiro-type host material, 5-[4-(1-naphthyl)phenyl]-spiro[fluorene-7,9'-benzofluorene] (BH-1PN) and three new dopants, namely, 5-[diphenylamino)phenyl]-spiro[fluorene-7,9'-benzofluorene] (BH-1TPA), 5-[4-(N-phenyl (m-tolyl)amino]-spiro[fluorene-7,9'-benzofluorene] (BH-1MDPA) and 5-[(N-phenyl)-2-naphthyl]amino-spiro[fluorene- 7,9'-benzofluorene] (BH-1NPA) were designed and successfully prepared using the Suzuki or amination reactions. The electroluminescence characteristics of BH-1PN as a blue host material doped with each of the blue dopants were evaluated. The structure of the device is ITO/DNTPD/NPB/BH-1PN:5% dopant/Alq3/Al-LiF. The device obtained from BH-1PN doped with diphenyl-[4-(2-[1,1;4,1]terphenyl-4-yl-vinyl)phenyl]-amine (BD-1) showed good color purity, efficiency, luminance, and current-density characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.693-696
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• 2011

Recently, amorphous oxide semiconductors (AOSs) based thin-film transistors (TFTs) have received considerable attention for application in the next generation displays industry. The research trends of AOSs based TFTs investigation have focused on the high device performance. The electrical properties of the TFTs are influenced by trap density. In particular, the threshold voltage ($V_{th}$) and subthreshold swing (SS) essentially depend on the semiconductor/gate-insulator interface trap. In this article, we investigated the effects of Ar plasma-treated $SiO_2$ insulator on the interfacial property and the device performances of amorphous indium gallium zinc oxide (a-IGZO) TFTs. We report on the improvement in interfacial characteristics between a-IGZO channel layer and gate insulator depending on Ar power in plasma process, since the change of treatment power could result in different plasma damage on the interface.

• Journal of the Korean Society of Safety
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• v.24 no.4
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• pp.104-110
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• 2009

In this driving simulation study, the impairing effects of various types of electronic devices usage(i. e., destination search by using in-vehicle navigation system, TV watching and dialing cellular phone) during driving on front-to-rear-end collision avoidance were investigated. Percentage of collisions, driving speeds when the drivers collided, and initial reaction time for collision avoidance were analyzed and compared as the dependent measures. The results indicated that (1) any types of electronic devices usage during driving induced more serious collision-related impairment than control condition where no additional task was required, and (2) in general, destination search task appeared to impair drivers collision avoidance performance more than the other task requirements in terms of percentage of collisions and initial reaction time for collision avoidance, but TV watching induced most serious collision impact. These results suggested that any types of electronic device usage could distract drivers attention from the primary task of driving, and be resulted in serious outcome in potentially risky situation of front-to-rear-end collision. In particular, mandatory use of eye-hand coordination and receiving feedback seemed to one of essential factor leading the drivers visual attentional distraction.