• Korean Journal of Materials Research
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• v.29 no.9
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• pp.532-541
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• 2019

Information and communication technologies are developing rapidly as IC chip size becomes smaller and information processing becomes faster. With this development, digital circuit technology is being widely applied to mobile phones, wireless LANs, mobile terminals, and digital communications, in which high frequency range of GHz is used. In high-density electronic circuits, issues of noise and EMC(Electro-Magnetic Compatibility) arising from cross talk between interconnects or devices should be solved. In this study, sheet-type electromagnetic wave absorbers that cause electromagnetic wave attenuation are fabricated using composites based on soft magnetic metal powder and silicon rubber to solve the problem of electromagnetic waves generated in wireless communication products operating at the frequency range of 2.4 GHz. Sendust(Fe-Si-Al) and carbonyl iron(Fe-C) were used as soft magnetic metals, and their concentrations and sheet thicknesses were varied. Using soft magnetic metal powder, a sheet is fabricated to exhibit maximum electromagnetic attenuation in the target frequency band, and a value of 34.2dB(99.9 % absorption) is achieved at the target frequency.

• International Journal of Advanced Culture Technology
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• v.7 no.1
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• pp.225-230
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• 2019

In order to improve performance for the size of the rat-race ring coupler, the CCL is used for the realization as the delay line. As realizing lower coupling coefficient, the ratio of the size-reduction for the CCL is enhanced. The CCL is alternated with ${\lambda}_g/4$ of the rat-race ring, and optimized two CCLs are inserted for the size-reduction. the coupling coefficient is 0.2, and electrical lengths of each CCL are $28.2^{\circ}$ and $21.7^{\circ}$. Designed rat-race ring using the CCL has the size of $18.76{\times}20.45mm^2$ and the size-reduction ratio of fabricated rat-race ring using the CCL has 76.8%. Also, fabricated rat-race ring is measured the insertion loss of 3.20dB at the center frequency of 2.45GHz and the 20dB bandwidth is 24.04%. Differenced magnitude and phase between threw port and coupled port are measured 0.1dB and $177.4^{\circ}$, respectively. These performances are almost same compared with the conventional rat-race ring. Suggested application of the CCL can be used various devices and circuits for the size-reduction.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.100-106
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• 2024

To generate the plasma required in dry cleaning processes, the plasma chamber must be supplied with a high-quality AC voltage with a voltage of more than 1 kV and a frequency of 400 kHz. In the existing research, many methods to supply high power have been studied, but how to improve the quality of the power for high-quality plasma has been relatively little studied. In this paper, we propose a study to improve the quality of RF power circuit for high-quality plasma generation in dry cleaning method. Existing methods in the environment of full-bridge-based RF power circuits must perform PWM duty control in the light load region. This causes distortions in the waveform, resulting in poor power quality, which directly leads to poor plasma quality. To solve these problems, a half-bridge switching method is proposed and the improvement in waveform quality is verified. To verify the feasibility of the design and control algorithm proposed in this paper, an RF power circuit prototype is fabricated and the proposed design and control method is verified through simulation and actual experiments under dummy load.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.115-122
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• 2014

In this paper, reliability is secured by sensing a post-program resistance of several tens of kilo ohms and restricting a read current flowing over an unblown eFuse within $100{\mu}A$ since RWL driver and BL pull-up load circuits using a regulated voltage of V2V ($=2V{\pm}10%$) are proposed to have a wide operating voltage range for eFuse OTP memory. Also, when a comparison of a cell array of 1 row ${\times}$ 32 columns with that of 4 rows ${\times}$ 8 columns is done, the layout size of 4 rows ${\times}$ 8 columns is smaller with $187.065{\mu}m{\times}94.525{\mu}m$ ($=0.01768mm^2$) than that of 1 row ${\times}$ 32 columns with $735.96{\mu}m{\times}61.605{\mu}m$ ($=0.04534mm^2$).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.55-62
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• 2005

In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM WLAN baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at $80\%$ of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945K. The real-time operation is verified and evaluated using a FPGA test system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.