• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
• /
• pp.1027-1029
• /
• 2004

In this paper, we have fabricated pentacene thin film transistors (TFTs) using polyvinylphenol (PVP) copolymer and cross-linked PVP as gate insulator on glass and plastic (PET) substrate. Depending on the density of PVP and cross-link material the performance has been changed. We obtained the best device performance with the mobility of 0.32cm2/V${\cdot}$sec and the on/off current ratio of 1.19${\times}$106 for the case of 10wt% PVP copolymer mixed with 5wt% poly (melamine-co-formaldehyde). Additionally using pentacene TFTs with the above PVP gate insulator, we fabricated the integrated circuits including inverter which produced the gain of 9.7.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
• /
• pp.212-216
• /
• 2001

Because conventional switching converters have been usually using unbalanced circuit topologies, parasitic capacitance between the drain/collector of an active switch and the frame ground through its heat sink may generate the common-mode conducted noise. We have proposed a balanced switching converter circuit, which is an effective way to reduce the common-mode conducted noise. As an example, a boost converter version of the balanced switching converter was presented and the mechanism of the common-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switching converter circuit and presents a buck-boost converter version of the balanced switching converter. The feature of common-mode noise reduction is confirmed by experimental results and the mechanism of the common-mode noise reduction is explained using equivalent circuits.

• ETRI Journal
• /
• 제30권5호
• /
• pp.729-734
• /
• 2008

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling-time constraints. This makes the use of traditional closed-loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast-settling response. The AGC has been implemented in a 0.35 ${\mu}m$ standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 ${\mu}s$.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1993년도 추계학술대회 논문집
• /
• pp.93-96
• /
• 1993

BiCMOS technology, which combines CMOS and bipolar technology, offers the possibility of achieving both very high density and high performance. In this paper, the characteristics of BiCMOS and CMOS circuits, especilly the delay time is studied. BiCMOS inverter, which has high drive ability because of bipolar transistor, drives high load capacitance and has low-power characteristics because the current flows only during switching transient just like the CMOS gate. BiCMOS inverter has the less dependence on load capacitance than CMOS inverter. SPICE that has been used for electronic circuit analysis is chosen to simulate these circuits and the characteristics is discussed.

• 대한전자공학회논문지
• /
• 제10권2호
• /
• pp.23-35
• /
• 1973

ECAP을 사용하여 직류, 교류, 과도현상에 대한 회로해석을 논하였으며 2단 가청주파 증폭기의 저주파 및 고주파 영역에서의 주파수 특성을 ECAP방식을 사용하여 해석하였다. 또한 근사식과 실험을 통하여 전류, 전압의 이득을 구하여 콤퓨터에 의한 값과 비교하여 본 결과 잘 일치함을 보였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
• /
• pp.231-234
• /
• 1989

In recent, due to the advanced development of the power semiconductor devices, the Digital Simulation becomes essential in order to investigate the behavior of the system before the manufacturing of the system by using computer for design and analysis of Power Electronic systems. This paper develope the program so-called PECA, which can be applied for the Power Electronic circuits composing of power transistors, thyristers, GTOs and power FET, etc. We consider transistor DC chopper circuit and prove the effectiveness of our program by both the experiment and simulation.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2002년도 전력전자학술대회 논문집
• /
• pp.330-333
• /
• 2002

The design of high power electronic circuits and the verification of the design by practical experiments are time and cost consuming. Recently power circuit simulation technique is developing to do it easily. However, most of the simulation has used the ideal switch model consists of passive component that can not describe the physical characteristics of semiconductor devices and cannot describe the switching transient state. For the design of such power electronic circuits by the simulation, the switching transients are very important. Therefore the simulation models must describe the switching transient and the stationary behavior as precisely as possible on the hand and as fast as possible the other hand. This paper introduces the application of the physical models of power devices that are developed by TUM(Technical University of Munich, Germany) for the power electronic circuit analysis.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
• /
• pp.635-638
• /
• 2005

An energy recovery sustaining driver with zero current switching to reduce switching losses and EMI is presented in this paper. The driver with designed snubber circuits reduces ringing voltage significantly on PDP so that the voltage rating of MOSFETs can be lower as well to reduce the cost of switches.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
• /
• pp.278-281
• /
• 1988

This paper realizes the multi-output truncated difference circuits using current mode CMOS, and presents the algorithm designing multi - valued logic functions of a given multivalued truth tables. This algorithm divides the discrete valued functions and the interval functions, and transforms them into the truncated difference functions. The transformed functions are realized by current mode CMOS. The technique presented here is applied to MOD4 addition circuit and GF(4) multiplication circuit.

• Journal of Power Electronics
• /
• 제2권2호
• /
• pp.139-145
• /
• 2002

Because conventional switching converters have been usually using unbalanced circuit topologies, parasitice between the drain/collertor of an active switch and frame ground through its heat sink may generate the commom-mode conducted noise. We have proposed a balanced switching converter circuit, whitch is an effective way to reduce the commom-mode converter version of the balanced switching converter was presented and the mechanism of the commom-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switch converter circuit and presents a buck-boost converter version of the blanced switching converter. The feature of common-mode niose reduction is confirmed by experimental resuits and the mechanisem of the commom-mode niose reduction is explained using equivalent circuits.