• 제목/요약/키워드: Electronic Circuits

검색결과 958건 처리시간 0.024초

Thai Phoneme Segmentation using Dual-Band Energy Contour

  • Ratsameewichai, S.;Theera-Umpon, N.;Vilasdechanon, J.;Uatrongjit, S.;Likit-Anurucks, K.
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -1
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    • pp.110-112
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    • 2002
  • In this paper, a new technique for Thai isolated speech phoneme segmentation is proposed. Based on Thai speech feature, the isolated speech is first divided into low and high frequency components by using the technique of wavelet decomposition. Then the energy contour of each decomposed signal is computed and employed to locate phoneme boundary. To verity the proposed scheme, some experiments have been performed using 1,000 syllables data recorded from 10 speakers. The accuracy rates are 96.0, 89.9, 92.7 and 98.9% for initial consonant, vowel, final consonant and silence, respectively.

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Analysis of LSI Circuits Coupled with RCG Interconnects - Asymptotic Method

  • A.Ushida;Ha, A.ttori;H.Sakaguchi;Y.Yamagami;Y.Nishio
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -1
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    • pp.70-73
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    • 2002
  • High frequency digital LSI circuits are usually composed of many sub-circuits coupled with interconnects. They sometimes causes serious problems of the fault switching by time-delays, crosstalks, reflections of signals and so on. Therefore, it is very important to develop a user-friendly simulator for solving these problems. Although a moment matching method is widely used as the reduction technique of interconnects, it may happen to arise erroneous results for evaluating the poles far from the origin. In this paper, we show an asymptotic method in the complex frequency-domain, where we calculate the exact poles and residues giving large effect to the transient responses. Then, the interconnects are replaced by the asymptotic equivalent circuits using the poles and residues. Thus, we can develop a users-friendly simulator using the equivalent circuits.

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전자식 형광등용 역율 개선 회로의 특성 비교 (The characteristic comparison of power factor correction circuits for electronic ballasts)

  • 박종연;조계현
    • 산업기술연구
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    • 제18권
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    • pp.165-172
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    • 1998
  • In recent years, various power factor correction(PFC) circuits for the electronic ballast have been proposed. And these circuits have difference characteristics each other. We have researched several PFC circuits of them. And operational principles and characteristics of PFC circuits are compared by the cost and the electrical performance. Finally, we established the reference for the evaluation of PFC circuits with performance and the price.

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RF MEMS Switches and Integrated Switching Circuits

  • Liu, A.Q.;Yu, A.B.;Karim, M.F.;Tang, M.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제7권3호
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    • pp.166-176
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    • 2007
  • Radio frequency (RF) microelectromechanical systems (MEMS) have been pursued for more than a decade as a solution of high-performance on-chip fixed, tunable and reconfigurable circuits. This paper reviews our research work on RF MEMS switches and switching circuits in the past five years. The research work first concentrates on the development of lateral DC-contact switches and capacitive shunt switches. Low insertion loss, high isolation and wide frequency band have been achieved for the two types of switches; then the switches have been integrated with transmission lines to achieve different switching circuits, such as single-pole-multi-throw (SPMT) switching circuits, tunable band-pass filter, tunable band-stop filter and reconfigurable filter circuits. Substrate transfer process and surface planarization process are used to fabricate the above mentioned devices and circuits. The advantages of these two fabrication processes provide great flexibility in developing different types of RF MEMS switches and circuits. The ultimate target is to produce more powerful and sophisticated wireless appliances operating in handsets, base stations, and satellites with low power consumption and cost.

형광등용 전자식 안정기에 적합한 수동 역률개선회로의 제안 및 특성 개선에 관한 연구 (Improved Passive Power Factor Correction Circuits of Electronic Ballasts for fluorescent lamps)

  • 채균;류태하;조규형
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 F
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    • pp.2795-2797
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    • 1999
  • Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

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Estimation of Transferred Power from a Noise Source to an IC with Forwarded Power Characteristics

  • Pu, Bo;Kim, Taeho;Kim, SungJun;Kim, Jong-Hyeon;Kim, SoYoung;Nah, Wansoo
    • Journal of electromagnetic engineering and science
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    • 제13권4호
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    • pp.233-239
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    • 2013
  • This paper proposes an accurate approach for predicting transferred power from a noise source to integrated circuits based on the characteristics of the power transfer network. A power delivery trace on a package and a printed circuit board are designed to transmit power from an external source to integrated circuits. The power is demonstrated between an injection terminal on the edge of the printed circuit board and integrated circuits, and the power transfer function of the power distribution network is derived. A two-tier calibration is applied to the test, and scattering parameters of the network are measured for the calculation of the power transfer function. After testing to obtain the indispensable parameters, the real received and tolerable power of the integrated circuits can be easily achieved. Our proposed estimation method is an enhancement of the existing the International Electrotechnical Commission standard for precise prediction of the electromagnetic immunity of integrated circuits.

웹 기반 하이브리드 전기전자회로 실험시스템의 구현 (Implementation of a Web-based Hybrid Experimental System for Electric and Electronic Circuits)

  • 김동식;최관순;문일현;이순흠
    • 컴퓨터교육학회논문지
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    • 제10권5호
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    • pp.53-60
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    • 2007
  • 학습효율의 향상을 위해 본 논문에서는 웹기반 가상실험시스템과 원격실험시스템을 적절하게 통합하여 전기전자회로에 대한 하이브리드 실험시스템을 구현하였다. 먼저, 전기/전자회로 실험에 대한 웹기반 가상실험실을 개발하여 개념학습, 가상실험, 평가등의 3개의 주요 세션과 그에 대한 관리시스템으로 구성하였다. 다음으로 가상실험을 진행하는 동안 발생할 수 있는 현실감의 부족성 문제를 해결하기 위해 전기전자회로에 대한 원격실험시스템을 구현하였다. 제안된 가상/원격실험시스템은 독립적인 형태로 사용될 수도 있지만, 학습효율을 극대화하기 위해서 두 개의 시스템을 통합하여 하이브리드 전기전자 실험시스템을 구현하였다.

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모듈형 플러그인 능동전력디커플링 회로를 위한 계통전압 추종 방법 (Grid Voltage Estimation Method for Modular Plug-in Active Power Decoupling Circuits)

  • 김동희;김정태;박성민;정교범
    • 전력전자학회논문지
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    • 제26권4호
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    • pp.294-297
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    • 2021
  • A grid voltage estimation method for modular plug-in active power decoupling (APD) circuits is proposed in this study as direct replacements of electrolytic capacitors. Since modular plug-in APD circuits cannot have additional grid voltage sensors and should be operated independently without information exchange with the front-end converter, it is impossible to obtain the phase information of the grid directly. Therefore, the proposed method uses the second-order harmonic component of the DC-link voltage to estimate the grid voltage necessary to control the APD circuit. By employing the proposed method, the concept of modular plug-in APD circuits can be realized and implemented without direct detection of the grid voltage. The experimental results based on hardware-in-the-loop simulation (HILS) validate the effectiveness of the proposed control method.

Investigation of Hetero - Material - Gate in CNTFETs for Ultra Low Power Circuits

  • Wang, Wei;Xu, Min;Liu, Jichao;Li, Na;Zhang, Ting;Jiang, Sitao;Zhang, Lu;Wang, Huan;Gao, Jian
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권1호
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    • pp.131-144
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    • 2015
  • An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of ${\Phi}_{M1}/{\Phi}_{M2}/{\Phi}_{M3}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.