• E2M - 전기 전자와 첨단 소재
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• 제7권6호
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• pp.473-480
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• 1994

The electron tunnel effect in polvimide LB films sandwiched between metal electrodes has been investigated in the present work by a study of both the elastic and inelastic tunneling components. By the results of elastic tunneling experiments in Au/Pl/Au tunneling junction, we can judge the height and thickness of tunnel barrier. The inelastic current in Inelastic Electron Tunneling Spectroscopy(IETS) is due to the interaction of the tunneling electron with the vibrational modes of the molecular species in the barrier. Measurements are done on Au/PI/Pb tunneling junctions. The spectra obtained are the second derivatives of the current-voltage characteristics of these junctions : specifically, d$^{2}$1/dV$^{2}$ as a function of voltage V. Because the energies measured by IETS can be directly compared to those measured by infrared and Raman spectroscopy, IR-RAS spectroscopy also measured for reference.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.544-546
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• 1995

Tunneling of an electron non-normally incident on a potential barrier is theoretically studied. Tunneling time and the position where an electron appears after the tunneling are derived using the phase time approach. The positions where photons appear after two-dimensional tunneling in a frustrated total internal reflection structure are also discussed.

• Bulletin of the Korean Chemical Society
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• 제26권11호
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• pp.1885-1888
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• 2005

• Bulletin of the Korean Chemical Society
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• 제23권1호
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• pp.71-74
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• 2002

The apparent barrier height for charge transfer through an interfacial water layer between a Pt/Ir tip and a gold surface has been measured using STM technique. The average thickness of the interfacial water layer inside an STM junction was controlled by the amount of moisture. A thin water layer on the surface was formed when relative humidity was in the range of 10 to 80%. In such a case, electron tunneling through the thin water layer became the majority of charge transfers. The value of the barrier height for the electron tunneling was determined to be 0.95 eV from the current vs. distance curve, which was independent of the tip-sample distance. On the other hand, the apparent barrier height for charge transfer showed a dependence on tip-sample distance in the bias range of 0.1-0.5 V at a relative humidity of approximately 96%. The non-exponentiality for current decay under these conditions has been explained in terms of electron tunneling and electrochemical processes. In addition, the plateau current was observed at a large tip-sample distance, which was caused by electrochemical processes and was dependent on the applied voltage.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1670-1676
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• 2014

This paper presents the modeling of Single Electron Transistor (SET) based on Physical model of a device and its equivalent circuit. The physical model is derived from Schrodinger equation. The wave function of the electrode is calculated using Hartree-Fock method and the quantum dot calculation is obtained from WKB approximation. The resulting wave functions are used to compute tunneling rates. From the tunneling rate the current is calculated. The equivalent circuit model discuss about the effect of capacitance on tunneling probability and free energy change. The parameters of equivalent circuit are extracted and optimized using genetic algorithm. The effect of tunneling probability, temperature variation effect on tunneling rate, coulomb blockade effect and current voltage characteristics are discussed.

• 한국전기전자재료학회논문지
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• 제17권2호
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• pp.196-200
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• 2004

Using polyimide Langmuir-Blodgett(LB) films as a tunneling harrier, we fabricated Au/Polyimide/1-layer arachidic acid/Pb structure in order to investigate electron transport properties through a junction. It was found that 9-layer polyimide LB films function as a good tunneling harrier in a study of current-voltage(I-V) chararteristics. And several peaks originating in the vibrational modes of the constituent molecules of 1-layer arachidic acid LB films were clearly observed in d$^2$V/dI$^2$- V corves.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.208-211
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• 1997

We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-gate is the lower-level gate and located ∼ 100${\AA}$ right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-Blockade oscillation is demonstrated at 15mK and its periodicity of 16.4mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.

• 대한전기학회논문지
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• 제45권1호
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• pp.159-163
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• 1996

Simulated electron tunneling time through a potential barrier is compared with theoretical phase time. For a GaAs/Al/sub 0.3/Ga/sub 0.7/As/GaAs potential barrier with 300 meV height and 3 nm or 5 nm width, simulations are performed with various average electron energies and momentum deviations. The simulation results become closer to the theoretical phase time as the average electron energy decreases and as the momentum deviation decreases. It is also shown that a barrier, which is due to the peak spectrum shift in the momentum space after tunneling. (author). refs., figs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.40-49
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• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.276-283
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• 2005

Magnetic tunneling transistor (MTT) device using the amorphous n-type Si semiconductor film for base and collector consisting of the [CoFe/NiFe](free layer) and Si(top layer) multilayers was used to study the spin-dependent hot electron magnetocurrent (MC) and tunneling magnetoresistance (TMR) at room temperature. A large MC of 40.2 % was observed at the emitter-base bias voltage ( $V_{EB}$ ) of 0.62 V. The increasing emitter hot current and transfer ratio ( $I_{C}$/ $I_{E}$) as $V_{EB}$ are mainly due to a rapid increase of the number of conduction band states in the Si collector. However, above the $V_{EB}$ of 0.62 V, the rapid decrease of MC was observed in amorphous Si-based MTT because of hot electron spin-dependent elastic scattering across CoFe/Si interfaces.