• Title/Summary/Keyword: Electromagnetic Topology

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Investigation of Rise Time and Overshoot in Pulse Transformers with Different Topologies for Electromagnetic Trigger of SCRs

  • Lv, Gang;Zeng, Dihui;Zhou, Tong
    • Journal of Power Electronics
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    • v.18 no.3
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    • pp.902-909
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    • 2018
  • This study investigates the influences of different core parameters on the dynamic performances, such as rise time and overshoot, in pulse transformers for the triggering circuit of SCRs. First, a simplified transformer equivalent circuit, which emerges from a standard transformer equivalent circuit, is developed to analyze the step response. Second, the relations between the dynamic performances and the parasitic parameters are calculated by the simplified equivalent circuit. Third, the variations of rise time and overshoot, which are vital to the stability of triggering SCRs, with different core parameters, such as mechanic dimensions and topologies, are comprehensively investigated by analyzing the parasitic parameters. Finally, prototype transformers are fabricated to experimentally validate the analysis. The presented method can practically instruct the design of a pulse transformer for triggering SCRs.

Analysis and Design of High Efficiency Feedforward Amplifier Using Distributed Element Negative Group Delay Circuit (분산 소자 형태의 마이너스 군지연 회로를 이용한 고효율 피드포워드 증폭기의 분석 및 설계)

  • Choi, Heung-Jae;Kim, Young-Gyu;Shim, Sung-Un;Jeong, Yong-Chae;Kim, Chul-Dong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.6
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    • pp.681-689
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    • 2010
  • We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

Totem-pole Bridgeless Boost PFC Converter Based on GaN FETs (GaN FET을 이용한 토템폴 구조의 브리지리스 부스트 PFC 컨버터)

  • Jang, Paul;Kang, Sang-Woo;Cho, Bo-Hyung;Kim, Jin-Han;Seo, Han-Sol;Park, Hyun-Soo
    • The Transactions of the Korean Institute of Power Electronics
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    • v.20 no.3
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    • pp.214-222
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    • 2015
  • The superiority of gallium nitride FET (GaN FET) over silicon MOSFET is examined in this paper. One of the outstanding features of GaN FET is low reverse-recovery charge, which enables continuous conduction mode operation of totem-pole bridgeless boost power factor correction (PFC) circuit. Among many bridgeless topologies, totem-pole bridgeless shows high efficiency and low conducted electromagnetic interference performance, with low cost and simple control scheme. The operation principle, control scheme, and circuit implementation of the proposed topology are provided. The converter is driven in two-module interleaved topology to operate at a power level of 5.5 kW, whereas phase-shedding control is adopted for light load efficiency improvement. Negative bias circuit is used in gate drivers to avoid the shoot-through induced by high speed switching. The superiority of GaN FET is verified by constructing a 5.5 kW prototype of two-module interleaved totem-pole bridgeless boost PFC converter. The experiment results show the highest efficiency of 98.7% at 1.6 kW load and an efficiency of 97.7% at the rated load.

Topology Optimization of Beam Splitter for Multi-Beam Forming Based on the Phase Field Design Method (페이즈 필드 설계법 기반의 다중 빔 형성을 위한 빔 분배기 위상최적설계)

  • Kim, Han-Min
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.32 no.3
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    • pp.141-147
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    • 2019
  • In this paper, a systematic beam splitter design for multi-beam forming is proposed. The objective of this research is to a design beam splitter that splits and focuses scattering microwaves into intense beams in multiple directions. It is difficult to split multi-beam to non-specific directions with theoretical approaches. Therefore, instead of using transformation optics(TO), which is a widely used process for controlling electromagnetic wave propagation, we used a systematic design process called the phase field design method to obtain an optimal topological structure of beam splitter. The objective function is to maximize the norm of electric field of the target areas of each direction. To avoid island structure and obtain the structure in one body, volume constraint is added to the optimization problem by using augmented Lagrangian. Target frequency is set to X-band 10GHz. The optimal beam splitter performed well in multi-beam forming and the transported electric energy of target areas improved. A frequency dependency test was conducted in the X-band to determine effective frequency range.

RF Collimator Design having Multi-Dielectric Structure using the Phase Field Design Method (페이즈필드 설계법을 이용한 다중 유전체 구조의 RF 콜리메이터 설계)

  • Go, Joohyun;Seong, Hong Kyoung;Kim, Hanmin;Park, Jinwoo;Yoo, Jeonghoon
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.31 no.1
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    • pp.47-52
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    • 2018
  • In this study, a collimator composed of multi-dielectric structures is designed using the phase field design method, a kind of topology optimization methods. It is also purposed to improve the mechanical-structural performance of a collimator by replacing previously used air regions with another dielectric material. Polypropylene and paraffin are selected as the dielectric materials for the design process taking manufacturability into account. The design objective is formulated by integrating the intensity of the electromagnetic field in the pre-determined target area to realize the collimating performance. The model for accurate numerical analysis was derived from the final result obtained from the design process through the simple cut-off method and it shows the improved performance of 105% compared with the free space wave propagation. For the designed model, the possibility of reverse transformation, the mechanical durability evaluation under the compression load, and the electromagnetic performance in the X-band range were also evaluated.

Design of Ultra Wide-Band CMOS Low Noise Amplifier (광대역 CMOS 저잡음 증폭기 설계)

  • Moon Jeong-Ho;Jeong Moo-Il;Kim Yu-Sin;Lee Kwang-Du;Park Sang-Gyu;Han Sang-Min;Kim Young-Hwan;Lee Chang-Seok
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.6 s.109
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    • pp.597-604
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    • 2006
  • An ultrawideband(UWB) $3.1{\sim}5.15$ GHz low-noise amplifier employing a novel input matching circuit and feedback topology are presented. The proposed UWB amplifier is Implemented in $0.18{\mu}m$ RF CMOS technology. Measurements show a NF of $3.4{\sim}3.9$ dB, a power gain of $12.8{\sim}14$ dB, better than -9.4 of input matching and, an input IP3 of -1 dBm, while comsuming only 14.5 mW of power.

10-Bit Full-Coverage Impedance Tuner Using a Directional Coupler and PIN Diodes (방향성 결합기 및 핀 다이오드 스위치를 이용한 10 비트 임피던스 튜너)

  • Lee, Dong-Kyu;Lee, Sang-Hyo;Kwon, Young-Woo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.7
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    • pp.698-703
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    • 2007
  • In this paper, a novel impedance tuner using a directional coupler is proposed. The design topology is analyzed by signal flow graph(SFG) and shows advantages compared with conventional single and double stub methods from the view points of easy implementation and wide tuning range, respectively. This impedance tuner consists of ten switches and its $2^{10}$ tuning points are distributed uniformly on the whole Smith chart. The measured maximum magnitude of the reflection coefficient is 0.9. And the fabricated impedance tuner has a wide bandwidth from 1.8 to 2.2 GHz. Using this impedance tuner, we did a load-pull measurement of a power transistor.

Negative Impedance Converter IC for Non-Foster Matching (비 포스터 정합을 위한 부성 임피던스 변환기 집적회로)

  • Park, Hongjong;Lee, Sangho;Park, Sunghwan;Kwon, Youngwoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.3
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    • pp.283-291
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    • 2015
  • In this paper, a negative impedance converter, the key element of non-Foster matching to enhance the bandwidth of matching high Q-factor passive element, is presented. Proposed negative impedance converter is implemented by the topology of Linvill's transistor negative impedance converter circuit. It is hard to forecast the operation of negative impedance circuit, because it is composed of gain element and positive feedback. Therefore the negative impedance circuit is implemented by hybrid type beforehand to check out the feasibility and it is designed by integrated circuit. The integrated circuit is fabricated by commercial $0.18{\mu}m$ SiGe BiCMOS process, and non-Foster matching is observed at 700~960 MHz band by cancelling the target reactance.

Improvement of Radiation Performance of Mobile Phone Antenna Using PIFA on U-Shaped Ground Plane (U-형 접지면 상에 배치된 평판형 역 F 안테나 구조를 이용한 휴대폰 단말기의 무선 성능 개선)

  • Lee, Jeong-Ho;Song, Jae-Kwan;Yook, Jong-Gwan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.1
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    • pp.90-97
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    • 2010
  • In this paper, we propose antenna topology and ground plane shape to improve the performance of PIFA (Planar Inverted F Antenna) which is built-in mobile phone. First, we designed the PIFA antenna consists of multiple radiators to provide multi-current paths. Then we designed U-shaped ground plane on the PCB under the antenna. The proposed antenna structure shows TRP/TIS improvement of 2.0 dB/3.7 dB for GSM and 2.2 dB/ 2.0 dB for DCS and 0.8 dB/1.5 dB for PCS and 1.3 dB/0.7 dB for WCDMA at the free space.

A 0.18-μm CMOS Low-Power and Wideband LNA Using LC BPF Loads (광대역 LC 대역 통과 필터를 부하로 가지는 0.18-μm CMOS 저전력/광대역 저잡음 증폭기 설계)

  • Shin, Sang-Woon;Seo, Yong-Ho;Kim, Chang-Wan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.1
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    • pp.76-80
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    • 2011
  • This paper has proposed a 3~5 GHz low-power and wideband LNA(Low Noise Amplifier), which has been implemented in a 0.18-${\mu}m$ CMOS technology. The proposed LNA has basically the noise-cancelling topology to achieve a balun-function, wideband input matching, and relative low noise figure. In addition, it has utilized a 2nd-order LC-band-pass filter(BPF) as its output load to achieve higher power gain and lower noise figure with the lowest dc power consumption among previously reported works. The proposed amplifier consumes only 3.94 mA from a 1.8 V supply voltage. The simulation results show a power gain of more than +17 dB, a noise figure of less than +4 dB, and an input IP3 of -15.5 dBm.