• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.215-219
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• 2019

Development of DC interruption technology is being studied actively for enhanced DC grid reliability and stability. In this study, coil type superconductor DC circuit breaker was proposed as DC interruption. It is integration technology that combined current-limiting technique using superconductor and cut-off technique using mechanical DC circuit breaker. Superconductor was applied to the coil type. In simulation, Mayr arc model was applied to realize the arc characteristic in the mechanical DC circuit breaker. PSCAD/EMTDC had used to model and perform the simulation. To find out the protection range of coil type superconductor DCCB, the working operation have analyzed based on the rated voltage of DCCB. The results confirmed that, according to apply the limiting device, the protection range was increased in twice. Therefore, the probability of failure of interruption has lowered significantly.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.136-139
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• 2003

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of signal amplifiers, a nonlinear circuit with diodes, and a bandpass filter Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s NRZ signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.20 no.4
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• pp.397-404
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• 2010

The use of equivalent circuit models of piezoelectric energy harvesters is inevitable when power circuitry including rectifying and smoothing circuit elements is connected to them for evaluating DC electrical outputs. This is because it is difficult to incorporate the electro-mechanical coupling resulting from the additional circuitry into the conventional finite element analysis. Motivated by this observation, we propose a method to accurately extract the equivalent circuit parameters by using commercially available FEM software such as ANSYS which provides three-dimensional AC piezoelectric analysis. Then the equivalent circuit can be analyzed by circuit simulators such as $SimPowerSystems^{TM}$ of MATLAB. While the previous works have estimated the circuit parameters by experimental measurements or by analytical solutions developed only for limited geometries and boundary conditions, the proposed method has no such limitation because piezoelectric energy harvesters of any shapes and boundary conditions can be treated in FEM software. For the verification of the proposed method, multi-modal AC electrical power output by using a corresponding equivalent circuit is compared with that by ANSYS. The proposed method is then shown to be very useful in the subsequent evaluation of DC electrical output which is obtained by attaching a bridge diode and a storage capacitor to a piezoelectric energy harvester.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• Journal of Electrical Engineering and Technology
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• v.7 no.5
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• pp.778-783
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• 2012

The synthetic short-circuit making test to adequately stress the circuit breaker has been specified as the mandatory test duty in the IEC 62271-100. The purpose of this test is to give the maximum pre-arcing energy during making operation. And this requires the making operation with symmetrical short-circuit current that is established when the breakdown between contact gap occurs near the crest of the applied voltage. Also, if the interrupting chamber of circuit breakers is designed as the type of common enclosure or the operation is made by the gang operated mechanism that three-phase contacts are operated by one common mechanism, three-phase synthetic making test is basically required. Therefore, several testing laboratories have developed and proposed their own test circuits to properly evaluate the breaker performance. With these technical backgrounds, we have developed the new alternative three-phase making circuit.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.4
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• pp.368-376
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• 2012

According to developed distributed generators, Solid State Circuit Breaker(SSCB) is essential for high power quality of DC Grid. In this paper, a simple and new structure of DC SSCB with a fast circuit breaker and fault current limiter is proposed. It can help to choice low specification of elements because of the limiting of fault current and achieve economic efficiency for minimizing auxiliary SCRs. Also all of SCRs have little switching loss because they operate under ZVS and ZCS. Through simulations and experiments of short-circuit fault, the performance characteristic of proposed circuit is verified and a guideline is so suggested that the DC SSCB is applied for a different DC grid using formulas.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.1
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• pp.12-18
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• 2014

This paper analyzes how to calculate the three phase short circuit current calculation procedures used in the IEC 60909 short circuit. It presented the new procedure of the fault current for the interrupting capacity of the circuit breaker. This procedure is applied to the future power system and calculates the fault current. Power demands are increased because of the growth of the economy for this reason, the fault current of the power system is largely increased and the fault current procedure for the proper interrupting capacity calculation of the existing or the new circuit breaker is essential. How to calculate the three phase short circuit current for ac electrical system and select the high voltage and low voltage circuit breaker based on IEC 60909 standards.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.8
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• pp.1532-1537
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• 2009

Nowadays the diversity and large-capacity of electric appliances are strong effect on electrical fires augment in an alarming way. But, as the inactive response characteristics of the existing RCD (Residual Current protective Device) used on low voltage power distribution lines, so control of overload and electric short circuit faults, major causes of electrical fires, are not enough. Therefore this paper is confirmed the unreliability of the existing RCD by electrical faults simulation and is proposed a auxiliary trip device of RCD by using a high precision current sensor (namely, reed switch) for the prevention of electrical disasters in low voltage power distribution lines caused by overload or electric short circuit faults. The sensitive reed switch in the proposed ATD (auxiliary trip device) exactly detects the increased magnetic flux with the overload or the short current caused by a number of electrical faults, and then rapidly cuts off the existing RCD. The proposed auxiliary trip device of RCD is confirmed the excellent characteristics in response velocity and accuracy in comparison with the conventional circuit breaker through various operation performance analysis. The proposed ATD can also prevent electrical disaster, like as electrical fires, which resulted from the malfunction and inactive response characteristics of the existing RCD.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.187-190
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• 2002

Plasma Display Panel(PDP) has been recognized as one of the most competitive display panel. Hence, the importance of PDP driving circuit is getting higher and higher. At the same time, it is strongly required for the driving circuit to be high efficiency, high stability, and cost effective one. In this work, a stable PDP driving circuit is developed by improving the circuit configuration. And the reliability and the productivity of the driving circuit are improved by using the Intelligent Power Module(IPM) technology. Finally operating characteristics of the developed IPM driving circuit are verified by using signal source board developed.

• ETRI Journal
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• v.28 no.2
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• pp.182-190
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• 2006

The circuit modeling of interdigitated capacitors fabricated by high-k low-temperature co-fired ceramic (LTCC) sheets was investigated. The s-parameters of each test structure were measured from 50 MHz to 10 GHz, and the modeling was performed using these measured sparameters up to the first resonant frequency. Each test structure was divided into appropriate building blocks. The equivalent circuit of each building block was composed based on the partial element equivalent circuit (PEEC) method. Modeling was executed to optimize the parameters in the equivalent circuit of each building block. The validity of the extracted parameters was verified by the predictive modeling for the test structures with different geometry. After that, Monte Carlo analysis and sensitivity analysis were performed based on the extracted parameters. The modeling methodology can allow a device designer to improve the yield and to save time and cost for the design and manufacturing of devices.