• 제목/요약/키워드: Electrical charge

검색결과 2,504건 처리시간 0.03초

High Performance CMOS Charge Pumps for Phase-locked Loop

  • Rahman, Labonnah Farzana;Ariffin, NurHazliza Bt;Reaz, Mamun Bin Ibne;Marufuzzaman, Mohammad
    • Transactions on Electrical and Electronic Materials
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    • 제16권5호
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    • pp.241-249
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    • 2015
  • Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.

Behavior of Residual Charges in Water-tree Degraded XLPE Sheets and Cable

  • Ebinuma, Yasumitsu;Masui, Noriaki
    • Transactions on Electrical and Electronic Materials
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    • 제7권5호
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    • pp.224-229
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    • 2006
  • Many studies have been done on the application of residual charge measurement in cable degradation diagnosis. In this paper, the behavior of residual charges measured with water-tree degraded XLPE sheets and cable are discussed. At charge injection process, the charge is injected by applying dc voltage as a conventional method, suddenly cut-off ac voltage or impulse voltage. Therefore the residual charge is influenced by the applying process. At charge release process, transient dc current flows when applying ac high voltage and also ac high voltage superimposed to dc low voltage. From the results, new diagnosis method is suggested.

A Modified Charge Balancing Scheme for Cascaded H-Bridge Multilevel Inverter

  • Raj, Nithin;G, Jagadanand;George, Saly
    • Journal of Power Electronics
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    • 제16권6호
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    • pp.2067-2075
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    • 2016
  • Cascaded H-bridge multilevel inverters are currently used because it enables the integration of various sources, such as batteries, ultracapacitors, photovoltaic array and fuel cells in a single system. Conventional modulation schemes for multilevel inverters have concentrated mainly on the generation of a low harmonic output voltage, which results in less effective utilization of connected sources. Less effective utilization leads to a difference in the charging/discharging of sources, causing unsteady voltages over a long period of operation and a reduction in the lifetime of the sources. Hence, a charge balance control scheme has to be incorporated along with the modulation scheme to overcome these issues. In this paper, a new approach for charge balancing in symmetric cascaded H-bridge multilevel inverter that enables almost 100% charge balancing of sources is presented. The proposed method achieves charge balancing without any additional stages or complex circuit or considerable computational requirement. The validity of the proposed method is verified through simulation and experiments.

Numerical Modeling of Charge Transport in Polymer Materials Under DC Continuous Electrical Stress

  • Hamed, Boukhari;Fatiha, Rogti
    • Transactions on Electrical and Electronic Materials
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    • 제16권3호
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    • pp.107-111
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    • 2015
  • Our work is based on the development of a numerical model to develop a methodology for predicting the aging and breakdown in insulation due to the dynamics of space charge packets. The model of bipolar charge transports is proposed to simulate space charge dynamic for high DC voltage in law-density polyethylene (LDPE), taking into account the trapping and detrapping of recombination phenomena, this model has been developed and experimentally validation. Theoretical formulation of the physical problem is based on the Poisson, the continuity and the transport equations as well as on the appropriate models for injection. Numerical results provide temporal and local distributions of the electric field, the space charge density for the different kinds of charges, conduction and displacement current densities, and the external current.

Spatio-temporal Charge Distribution in Electric Double Layer Capacitors observed by pulsed Electro Acoustic Method

  • Sung, Youl-Moon
    • Transactions on Electrical and Electronic Materials
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    • 제8권4호
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    • pp.182-187
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    • 2007
  • The use of the pulsed electro acoustic (PEA) method allowed us to perform the direct observations of spatio-temporal charge distributions in Electric double layer capacitors (EDLCs) based on polarizable nanoporous carbonaceous electrode. The negative charge density became the maximum, about $205C/m^3$ at the region where was near to collector layer in EDLCs for case $V_{DC}=2.5V$, while the positively charged density became the maximum, about $61.1C/m^3$ at the region where it was located around the cathode layer. The performance of the best sample was found to be better in terms of the charge density (Cs) and specific energy ($E_s$) with a maximum value of ${\sim}8.4F/g$ and 26 Wh/kg. The $C_s$ obtained from the PEA method agreed well with that from the energy conversion method. The PEA measurement used here is a very useful method to quantitively investigates the spatio-temporal charge distribution in EDLCs.

Improved Memory Characteristics by NH3 Post Annealing for ZrO2 Based Charge Trapping Nonvolatile Memory

  • Tang, Zhenjie;Zhao, Dongqiu;Li, Rong;Zhu, Xinhua
    • Transactions on Electrical and Electronic Materials
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    • 제15권1호
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    • pp.16-19
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    • 2014
  • Charge trapping nonvolatile memory capacitors with $ZrO_2$ as charge trapping layer were fabricated, and the effects of post annealing atmosphere ($NH_3$ and $N_2$) on their memory storage characteristics were investigated. It was found that the memory windows were improved, after annealing treatment. The memory capacitor after $NH_3$ annealing treatment exhibited the best electrical characteristics, with a 6.8 V memory window, a lower charge loss ~22.3% up to ten years, even at $150^{\circ}C$, and excellent endurance (1.5% memory window degradation). The results are attributed to deep level bulk charge traps, induced by using $NH_3$ annealing.

3차원 전하 중첩법용 나선 전하의 특성에 관한 연구 (A Study on A Spiral Charge for 3 Dimensional Charge Simulation Method)

  • 민석원;박은서;송기현
    • 조명전기설비학회논문지
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    • 제15권4호
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    • pp.31-36
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    • 2001
  • 본 논문은 765[kV] 송전선로의 풍소음 저감용 spiral rod의 전계를 계산하기 위해서 3차원 전하중첩법용 나선 전하의 특성에 관해 연구하였다. 본 연구에서 나선전하를 정현 함수 전하로 모의하는 것 보다 상수전하로 모의한 것이 전위오차가 적었고, 상수전하를 한 개로 모의하는 것 보다 2개를 배치하여 계산했을 때 spiral rod의 전하를 가장 잘 모의할 수 있는 것으로 나타났다.

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공기층을 가진 저밀도 폴리에틸렌에서의 전도특성과 공간전하 효과 (Effects of Space Charge on Conduction Mechanism in Low density Polyethylene with Air Gap)

  • 박희웅;권윤혁;전승익;황보승;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 D
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    • pp.1438-1440
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    • 1998
  • In this work, simultaneous measur of space charge and conduction current was c out in LDPE with air gap by Pulsed-Electro-Aco Method. Also, effect of long time charging at con electric field on the formation of space charge conduction was investigated. From the experim results. we knew that the homo space charge formed near the dielectric surfaces and moving the bulk of dielectric as the electric field elevated. This was related with the deep traps b carriers and de trapping by Poole-field lowering conduction current was coincident with the Pool emission. From the long time charging experimen obtained the results that the negative space was moving into the dielectric bulk as the cha continued and the positive space charge accumulated at upper surface of LDPE.

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Process-Variation-Adaptive Charge Pump Circuit using NEM (Nano-Electro-Mechanical) Relays for Low Power Consumption and High Power Efficiency

  • Byeon, Sangdon;Shin, Sanghak;Song, Jae-Sang;Truong, Son Ngoc;Mo, Hyun-Sun;Lee, Seongsoo;Min, Kyeong-Sik
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권5호
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    • pp.563-569
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    • 2015
  • For some low-frequency applications such as power-related circuits, NEM relays have been known to show better performance than MOSFETs. For example, in a step-down charge pump circuit, the NEM relays showed much smaller layout area and better energy efficiency than MOSFETs. However, severe process variations of NEM relays hinder them from being widely used in various low-frequency applications. To mitigate the process-variation problems of NEM relays, in this paper, a new NEM-relay charge pump circuit with the self-adjustment is proposed. By self-adjusting a pulse amplitude voltage according to process variations, the power consumption can be saved by 4.6%, compared to the conventional scheme without the self-adjustment. This power saving can also be helpful in improving the power efficiency of the proposed scheme. From the circuit simulation of NEM-relay charge pump circuit, the efficiency of the proposed scheme is improved better by 4.1% than the conventional.

High Performance Charge Pump Converter with Integrated CMOS Feedback Circuit

  • Jeong, Hye-Im;Park, Jung-Woong;Choi, Ho-Yong;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • 제15권3호
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    • pp.139-143
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    • 2014
  • In this paper, an integrated low-voltage control circuit is introduced for a charge pump DC-DC boost converter. By exploiting the advantage of the integration of the feedback control circuit within CMOS technology, the charge pump boost converter offers a low-current operation with small ripple voltage. The error amplifier, comparator, and oscillator in the control circuit are designed with the supply voltage of 3.3 V and the operating frequency of 1.6~5.5 MHz. The charge pump converter with the 4 or 8 pump stages is measured in simulation. The test in the $0.35{\mu}m$ CMOS process shows that the load current and ripple ratio are controlled under 1 mA and 2% respectively. The output-voltage is obtained from 4.8 ~ 8.5 V with the supply voltage of 3.3 V.