• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.244-244
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• 2010

Doping process of crystalline silicon solar cell process is very important which is as influential on efficiency of solar. Doping process consists of pre -deposition and diffusion. Each of these processes is important in the process temperature and process time. Through these process conditions variable, p-n junction depth can be controled to low and high. In this paper, we studied a optimized doping pre-deposition temperature for high solar cell efficiency. Using a $200{\mu}m$ thickness multi-crystalline silicon wafer, fixed conditions are texture condition, sheet resistance($50\;{\Omega}/sq$), ARC thickness(80nm), metal formation condition and edge isolation condition. The three variable conditions of pre-deposition temperature are $790^{\circ}C$, $805^{\circ}C$ and $820^{\circ}C$. In the $790^{\circ}C$ pre-deposition temperature, we achieved a best solar cell efficiency of 16.2%. Through this experiment result, we find a high efficiency condition in a low pre-deposition temperature than the high pre-deposition temperature. We optimized a pre-deposition temperature for high solar cell efficiency.

• 한국전기전자재료학회논문지
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• 제30권7호
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• pp.407-412
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• 2017

This paper introduces a biocompatible packaging system for implantable medical device having a hermetic sealing, such that a perfect physical and chemical isolation between electronic medical system and human body (including tissue, body fluids, etc.) is obtained. The hermetic packaging includes an electronic MEMS pressure sensor, power charging system, and bluetooth communication system to wirelessly measure variation of capacitance. The packaging was acquired by Quartz direct bonding and $CO_2$ laser welding, with a size of width $ 6cm{\times}length\;10cm{\times}lheight\;3cm$. Hermetic sealing of the packaged system was tested by changing the pressure in a hermetic chamber using a precision pressure controller, from atmospheric to 900 mmHg. We found that the packaged system retained the same count or capacitance values with sensor 1 - 25,500, sensor 2 - 26,000, and sensor 3 - 20,800, at atmospheric as well as 900 mmHg pressure for 5 hours. This result shows that the packaging method has perfect hermetic sealing in any environment of the human body pressure.

• 한국전자파학회논문지
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• 제16권10호
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• pp.989-994
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• 2005

위성통신 시스템의 초고주파 스위치 메트릭스(MSM)를 위한 MMIC 스위치 칩을 InGaAs/GaAs p-HEMT 공정을 이용하여 설계 및 제작하였다. MMIC 스위치는 on과 off상태에서 우수한 입출력 반사계수를 위해 흡수형으로 설계되었다. 또한, 스위치 칩의 크기를 줄이기 위해 MIM 커패시터와 spiral 인덕터의 집중소자를 이용하여 3 GHz 대역에서의 ${\lambda}/4$ 임피던스 변환기를 구현하였다. 설계된 MMIC 스위치는 $3.2\~3.6\;GHz$ 대역에서 사용할 수 있으며 $1.6\;mm{\times}1.3\;mm$의 칩 크기를 갖는다. On-wafer 측정 결과, 2 dB 이하의 삽입 손실과 56.8 dB 이상의 격리도 특성을 나타내었다. 이와 같은 측정 결과는 시뮬레이션 결과와 잘 일치하는 것이다.

• 한국전자파학회논문지
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• 제27권8호
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• pp.709-716
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• 2016

본 논문에서는 온도변화에 둔감한 전기적 특성을 가지는 원격무선통신시스템용 듀플렉서 모듈을 제안하였다. 지상에서 자유공간을 비행하는 유도탄에 유도정보를 송신하기 위한 시스템에서의 듀플렉서 모듈은 높은 내전력 특성뿐만 아니라, 낮은 삽입손실, 높은 송수신대역 상호격리도, 고조파 성분 억제 기능이 요구된다. 제안된 듀플렉서 모듈은 하나의 안테나 포트로 연결되는 송신대역 대역통과필터와 수신대역 대역통과필터, 송신측 출력전력을 점검하는 평면형 커플러, 전력증폭기 및 동축 공동 공진기의 고조파 성분들을 감쇠하기 위한 저역통과필터로 구성된다. 온도변화에 따른 주파수 편이량을 최소로 설계하기 위해 공진기의 재질과 치수를 3D EM 시뮬레이션을 통해 결정하였다. 제작품의 측정결과와 시뮬레이션 결과가 잘 부합하였고, 유도무기체계뿐만 아니라, 소형 기지국시스템과 같은 민수분야에도 적용이 가능하리라 판단된다.

• 마이크로전자및패키징학회지
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• 제23권4호
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• pp.31-34
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• 2016

System In Package (SiP) is getting popular and momentum for the recent wearable, IoT and connectivity application apart from mobile phone. This is driven by market demands of cost competitive, lighter and smaller/thinner and higher performance. As one of many semiconducting assembly products, Leadframe product has been widely used for low cost solution, light/ small and thin form factor. But It has not been applied for SiP although Leadframe product has many advantages in cost, size and reliability performance. SiP is mostly based on laminate substrate and technically difficult on Leadframe substrate because of a limitation in SMT performance. In this paper, Leadframe based SiP product has been evaluated about key technical challenges in SMT performance and electrical shield technology. Mostly Leadframe is considered not available to apply EMI shield because of tie-bar around package edge. In order to overcome two major challenges, connection bars were deployed properly for SMT pad to pad and additional back-side etching was implemented after molding process to achieve electrical isolation from outer shield coating. This product was confirmed assembly workability as well as reliability.

• 한국전자파학회논문지
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• 제23권10호
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• pp.1128-1136
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• 2012

본 연구에서는 기존의 기계적 조향 방식에 의한 이동 통신 서비스 음영 지역 문제점을 개선하기 위해서 배열 안테나 빔 패턴의 null-steering 기법에 기반한 전기적 빔 조향 장치를 연구하였다. 특히, 하향 $-10^{\circ}{\sim}0^{\circ}$ 이내에서 빔 조향이 가변될 수 있도록 기지국 안테나 수직 빔 패턴의 $-30^{\circ}{\sim}0^{\circ}$ 범위에 존재하는 null을 제거하여 하향 방향에서 전파 음영을 개선하였다. 이때 안테나의 요구 사양은 하향 조향각 조절 범위 내에서 14.5 dBi의 이득과 부엽 세기는 -18 dB 이하로 억제되어야 한다. 또한, 편파의 격리도는 30 dB 이상을 나타내어야 한다. 본 연구의 타당성을 보이기 위해 W-CDMA용 기지국 안테나 및 빔 조향 장치를 설계 제작하여 그 유용성을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 센서학회지
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• 제1권2호
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• pp.131-145
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• 1992

본 논문은 SOI트랜스듀서 및 회로를 위해, Si 직접접합과 M-C국부연마법에 의한 박막SOI구조의 형성 공정을 기술한다. 또한, 이러한 박막SOI의 전기적 및 압저항효과 특성들을 SOI MOSFET와 cantilever빔으로 각각 조사했으며, bulk Si에 상당한다는 것이 확인되었다. 한편, SOI구조를 이용한 두 종류의 압력트랜스듀서를 제작 및 평가했다. SOI구조의 절연층을 압저항의 유전체분리층으로 이용한 압력트랜스듀서의 경우, $-20^{\circ}C$에서 $350^{\circ}C$의 온도범위에 있어서 감도 및 offset전압의 변화는 자각 -0.2% 및 +0.15%이하였다. 한편, 절연층을 etch-stop막으로 이용한 압력트랜스듀서에 있어서의 감도변화를 ${\pm}2.3%$의 표준편차 이내로 제어할 수 있다. 이러한 결과들로부터 개발된 SDB공정으로 제작된 SOI구조는 집적화마이크로트랜스듀서 및 회로개발에 많은 장점을 제공할 것이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.118-118
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• 2008

The oxide CMP has been applied to interlayer dielectric(ILD) and shallow trench isolation (STI) in chip fabrication. Recently the slurry used in oxide CMP being changed from silica slurry to ceria (cerium dioxide) slurry particularly in STI CMP, because the material selectivity of ceria slurry is better than material selectivity of silica slurry. Moreover, the ceria slurry has good a planarization efficiency, compared with silica slurry. However ceria abrasives make a material removal rate too high at the region of wafer center. Then we focuses on why profile of material removal rate is convex. The material removal rate sharply increased to 3216 $\AA$/min by $4^{th}$ run without conditioning. After $4^{th}$ run, material removal rate converged. Furthermore, profile became more convex during 12 run. And average material removal rate decreased when conditioning process is added to end of CMP process. This is due to polishing mechanism of ceria. Then the ceria abrasive remains at the pad, in particular remains more at wafer center contacted region of pad. The field emission scanning electron microscopy (FE-SEM) images showed that the pad sample in the wafer center region has a more ceria abrasive than in wafer outer region. The energy dispersive X-ray spectrometer (EDX) verified the result that ceria abrasive is deposited and more at the region of wafer center. Therefore, this result may be expected as ceria abrasives on pad surface causing the convex profile of material removal rate.

• 전기학회논문지
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• 제62권6호
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• pp.798-802
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• 2013

In a conventional DC power supply used for CO2 laser, the circuit elements such as a rectifier bridge, a current-limiting resistor, a high voltage switch, energy storage capacitors ans a high-voltage isolation transformer using high turn ratio are necessary. Consequently, those supplies are expensive and require a large space. Thus, laser resonator and power supply should be optimally designed. In this paper, we propose a new power supply using high frequency resonance phenomena for CW(Continuous wave) CO2 laser (maximum output of 23W with discharge length of 450mm). It consists of a transformer including leakage inductance, magnetizing inductance and half-bridge converter, a three-stage Cockcroft-Walton and PFC(Power factor correction) circuit. The output ripple voltage can be controlled the minimum of 0.24% under the high frequency switching of 231kHz. Furthermore, the output efficiency was improved to 16.4% and the laser output stability of about 5.6% was obtained in this laser system.