• Journal of the Korea Society for Simulation
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• v.22 no.4
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• pp.93-98
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• 2013

In this paper, the proposed shallow trench isolation structures for high threshold voltage for very large scale and ultra high voltage integrated circuits MOSFET were simulated. Physically based models of hot-carrier stress and dielectric enhanced field of thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated devices over an extended range of stress biases and ambient temperatures. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2594-2599
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• 2003

We consider some problems of the Modified SPRT(Sequential Probability Ratio Test) method for fault detection and isolation of inertial redundant sensor systems and propose an Advanced SPRT method to solve the problems of the Modified SPRT method. One problem of the Modified SPRT method to apply to inertial sensor system comes from the effect of inertial sensor errors such as misalignment, scale factor error and sensor bias in the parity vector, which make the Modified SPRT method hard to be applicable. The other problem is due to the correlation of parity vector components which may induce false alarm. We use a two-stage Kalman filter to remove effects of the inertial sensor errors and propose the modified parity vector and the controlled parity vector which removes the effect of correlation of parity vector components. The Advanced SPRT method is derived form the modified parity vector and the controlled parity vector. Some simulation results are presented to show the usefulness of the Advanced SPRT method to redundant inertial sensor systems.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.1
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• Journal of information and communication convergence engineering
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• v.22 no.1
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• pp.14-22
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• 2024

This study presents the design of a Wilkinson power divider for three-way output ports (WPD3OP), which incorporates a defected ground structure (DGS). An asymmetric power divider is integrated into the output ports of the conventional Wilkinson power divider (WPD), establishing a three-way output port configuration. The DGS introduces periodic or irregular patterns into the ground plane to suppress unwanted electromagnetic wave propagation, and its incorporation can enhance the performance of the power divider, in terms of the power-division ratio, isolation, and bandwidth, by reducing spurious resonances. The proposed design algorithm for an asymmetric power divider for three-way output ports is analyzed via circuit simulations using High-Frequency Simulation Software (HFSS). The results verify the validity of the proposed method. The analysis of the WPD3OP integrated with DGS certifies the achievement of a center frequency of 2 GHz. This confirmation is supported by schematic ideal design simulation results and measurements encompassing insertion losses, return losses, and isolation.

• Journal of Magnetics
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• v.19 no.4
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• pp.399-403
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• 2014

We designed an ultra-high frequency (UHF: 300MHz to 3 GHz) ferrite circulator to investigate magnetic parameters, which are suitable for a self-biased GHz circulator design. The size of the ferrite disk was 1.58 mm in thickness and 13.5 mm in diameter. The saturation magnetization ($4{\pi}M_s$) of 3900 Gauss, internal magnetic field ($H_{in}$) of 1 kOe, and ferromagnetic linewidth (${\Delta}H$) of 354 Oe were used in circulator performance simulation. The simulation results show the isolation of 36.4 dB and insertion loss of 2.76 dB at 2.6 GHz and were compared to measured results. A Ni-Zn ferrite circulator was fabricated based on the above design parameters. An out-of-plane DC magnetic field ($H_0$) of 4.8 kOe was applied to the fabricated circulator to measure isolation, insertion loss, and bandwidth. Experimental magnetic parameters for the ferrite were $H_{in}$ of about 1.33 kOe and $4{\pi}M_s$ of 3935 Gauss. The isolation 43.9 dB and insertion loss of 5.6 dB measured at 2.5 GHz are in close agreement with the simulated results of the designed ferrite circulator. Based on the simulated and experimental results, we demonstrate that the following magnetic parameters are suitable for 2 GHz self-biased circulator design: $4{\pi}M_r$ of 3900 Gauss, $H_a$ of 4.5 kOe, $H_c$ greater than 3.4 kOe, and ${\Delta}H$ of 50 Oe.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.248-251
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• 1999

Recently, according to developing industry and life style, power consumption have been increased year after year. Currently these much power demand from power consumer is weakening the allowable power reverse margin in summer. As on of the remedies about this problem, the small scale grid-connected photovoltaic system is considered for auxiliary power source. Generally, grid-connected inverter have a isolation transformer for electrical isolation from utility. This paper propose transformerless system topology an inquiry the validity using simulation.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2014-2016
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• 2003

A new residual generation scheme that can be employed in the process fault detection and isolation systems for linear (control) systems is suggested. The scheme is very simple, but provides the same information for the detection and isolation of the anticipated faults as the conventional multiple observer based schemes. Application results show the practical feasibility of the proposed scheme.

• Journal of Advanced Navigation Technology
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• v.18 no.4
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• pp.359-363
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• 2014

This paper presents the design and performance of an unequal divider with physical separation and electrical isolation. This divider has a series $18{\Omega}$ resistor and 0.7 pF capacitor circuit between two quarter-wave transmission lines at half phase angle from input terminal. This design method was improved a physical isolation between output ports and easy connected other circuit because of unnecessary of extra transmission line. To show the validity of the unequal divider with complex isolation components, a 4:1 ratio unequal divider was designed and measured at center frequency of 2 GHz. The measured divider performances have the return loss of 17 dB, insertion loss of 1.5 dB and 7.7 dB, and isolation of 18 dB. Its performance is in good agreement with the simulated results.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.1
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• pp.30-34
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• 2005

This study shows the lasing characteristics of InGaAs/InGaAsP multiple-quantum-well waveguide-type depleted optical thyristor (DOT) using the vertical window. The measured switching voltage and current are 3.36 V and 10 ㎂, respectively. The lasing threshold current is 131 mA at 25 ℃. The output peak wavelength is 1570 nm at a bias current of 1.22 Ith and there is not input signal anymore in the output port. The vertical injection depleted optical thyristor - laser diode (VIDOT-LD) using the vertical-injection structure shows very good isolation between input and output signal.