• 제목/요약/키워드: Efficiency of Power Dissipation

검색결과 93건 처리시간 0.024초

변형가공도를 이용한 AI 5083 합금의 고온변형거동 (High Temperature Deformation Behavior of Al 5083 Alloy Using Deformation Processing Maps)

  • 고병철;김종현;유연철
    • 소성∙가공
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    • 제7권5호
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    • pp.450-458
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    • 1998
  • The high temperature deformation behavior of Al 5083 alloy has been studied in the temperature range of 350 to 520 ${\circ}C$ and strain rate range of 0.2 to 3.0/sec by torsion test. The strain rate sensitivity(m) of the material was evaluated and used for estabilishing power dissipation maps following the dynamic material model. These maps show the variation of efficiency of power dissipation(${\eta}$=2m/(2m+1)) with temperature and strain rate. Hot restoration of dynamic recrystallization (DRX) was analyzed from the flow curve, deformed microstructure, and processing maps during hot deformation. Also, the effect of deformation strain on the efficiency of power dissipation of the alloy was analysed using the processing maps. Moreover relationship between the hot-ductility and efficiency of power dissipation of the alloy depending on thmperature and strain rate was studied using the Zener-Hollomon parameter(Z=${\varepsilon}$exp(Q/RT) It is found that the maximum efficiency of power dissipation for DRX in Al 5083 alloy is about 74.6 pct at the strain of 0.2. The strain rate and temperature at which the efficiency peak occurred in the DRX domain is found to be ∼0.1/sec and ∼450${\circ}C$ respectively.

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도시형 자기부상열차 전력 측정 (Measuring Power Dissipation for Urban Maglev Vehicle)

  • 박정웅;김봉섭;이장열;김행구
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
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    • pp.3092-3098
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    • 2011
  • This paper deals with analysis of measuring power dissipation when Maglev is running. With the various running scenarios for Maglev, power dissipation was measured and a comparative analysis of it and wheel-on rails were carried out. The purpose of this paper is to confirm the efficiency and economics on operation of Maglev and reflect detail design later. When the running scenarios of Maglev are the status of landing on and levitation, running at rated acceleration and deceleration and according to changes of velocity, the power dissipation was measured. The measured results are analyzed considering with apparent electric power and active power, reactive power and power factor etc. Due to the limited test track condition, it is very limited to compare and analyze Maglev and general trains. Nevertheless, It is a task of great significance to identify the efficiency and economics on operating Maglev through the results of measuring power dissipation. In the future, measuring power dissipation through more various scenarios will be carried out, and the results will be reflected the design.

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A Twin Symbol Encoding Technique Based on Run-Length for Efficient Test Data Compression

  • Park, Jae-Seok;Kang, Sung-Ho
    • ETRI Journal
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    • 제33권1호
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    • pp.140-143
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    • 2011
  • Recent test data compression techniques raise concerns regarding power dissipation and compression efficiency. This letter proposes a new test data compression scheme, twin symbol encoding, that supports block division skills that can reduce hardware overhead. Our experimental results show that the proposed technique achieves both a high compression ratio and low-power dissipation. Therefore, the proposed scheme is an attractive solution for efficient test data compression.

Scan Cell Grouping Algorithm for Low Power Design

  • Kim, In-Soo;Min, Hyoung-Bok
    • Journal of Electrical Engineering and Technology
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    • 제3권1호
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    • pp.130-134
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    • 2008
  • The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

Optimization of Bidirectional DC/DC Converter for Electric Vehicles Based On Driving Cycle

  • Yutao, Luo;Feng, Wang
    • Journal of Electrical Engineering and Technology
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    • 제12권5호
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    • pp.1934-1944
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    • 2017
  • As a key component of high-voltage power conversion system for electric vehicles (EVs), bidirectional DC/DC (Bi-DC/DC) is required to have high efficiency and light weight. Conventional design methods optimize the Bi-DC/DC at the maximum power dissipation point (MPDP). For EVs application, the work condition of the Bi-DC/DC is not strict as the MPDP, where the design method using MPDP may not be optimal during travel of EVs. This paper optimizes the Bi-DC/DC converter targeting efficiency and weight based on the driving cycle. By analyzing the two-phase interleaved Bi-DC/DC for hybrid energy storage systems (HESS) of EVs, its power dissipation is calculated, and an efficiency model is derived. On this basis, weight models of capacitor, inductor and heat sink are built, as well as a dynamic temperature model of heat sink. Based on these models, a method using New European Driving Cycle (NEDC) for optimal design of Bi-DC/DC which simultaneously considered efficiency and weight is proposed. The simulation result shows that compare with conventional optimization methods revealed that the optimization approach based on driving cycle allowed significant weight reduction while meeting the efficiency requirements.

시스템 온 칩(system-on-a-chip) 내부 코어들의 전력소모 변화를 고려한 새로운 테스트 스케쥴링 알고리듬 설계 (A Novel Test Scheduling Algorithm Considering Variations of Power Consumption in Embedded Cores of SoCs)

  • 이재민;이호진;박진성
    • 디지털콘텐츠학회 논문지
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    • 제9권3호
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    • pp.471-481
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    • 2008
  • 전력소모를 고려한 테스트 스케줄링은 회로의 복잡도가 높은 SoC 시스템을 테스트할 경우 제한된 전력 소모량 내에서 고장 검출율을 높일 수 있고 테스트 시간을 단축 할 수 있는 효과적인 방법이다. 본 논문에서는 제한된 전력소모량 내에서 효율적으로 테스트를 수행하기 위한 테스트 자원의 모델링 방법 및 테스트 스케줄링 알고리듬을 제안하고 그 유효성을 검증한다. 테스트 자원의 모델링 방법으로는 전력사용량의 최고점과 차고점을 이용한 방법 및 소모 전력의 변화량에 따라 테스트 자원을 분할하는 방법을 제시한다. 또한 테스트 자원과 코어의 상관관계를 이용하여 동시 사용가능한 최대 코어 수를 생성하는 확장나무성장 그래프 생성 알고리듬 및 전력의 최적화가 가능한 전력 소모량 변이 그래프 생성 알고리듬으로 구성된 휴리스틱(heuristic) 테스트 스케줄링 알고리듬을 제안하고 이전의 알고리듬과 비교한다.

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Optical Modeling for Polarization-dependent Optical Power Dissipation of Thin-film Organic Solar Cells at Oblique Incidence

  • Kim, Jungho;Jung, Sungyeop;Jeong, Inkyung
    • Journal of the Optical Society of Korea
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    • 제16권1호
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    • pp.6-12
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    • 2012
  • We present the optical models and calculation results of thin-film organic solar cells (OSCs) at oblique incidence of light, using the transfer matrix method. The simple expression for the optical power dissipation is derived at oblique incidence for s- and p-polarized light. The spatial distribution of the electric field intensity, the optical power density, and the optical power dissipation are calculated in both s- and p-polarized light with respect to the incidence angle. We identify how the light absorption efficiency for p-polarized light becomes relatively larger than that for s-polarized light as the incidence angle increases.

압축기 갭 유로 형상에 따른 압축기 EER 향상 (Improvement of Compressor EER Based on Shape of Gap Flow Passage)

  • 한상혁;이영림
    • 한국기계가공학회지
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    • 제21권3호
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    • pp.63-69
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    • 2022
  • Compressor efficiency must be improved to reduce refrigerator power consumption. In this study, the heat dissipation rate through the compressor housing is increased via gap flow passages between the compressor body and housing. Four types of gap flow passages are considered for achieving the maximum heat-dissipation rate. In addition, thermal analysis is performed to examine the effect of increased heat dissipation rate on the energy efficiency ratio (EER). The results show that the heat dissipation rate, compressor superheat, and compressor EER increased by up to approximately 52%, 3 ℃, and approximately 1%, respectively.

Seismic behavior of energy dissipation shear wall with CFST column elements

  • Su, Hao;Zhu Lihua;Wang, Yaohong;Feng, Lei;Gao, Zeyu;Guo, Yuchen;Meng, Longfei;Yuan, Hanquan
    • Steel and Composite Structures
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    • 제43권1호
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    • pp.55-66
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    • 2022
  • To develop high-efficiency lateral force resistance components for high-rise buildings, a novel energy dissipation shear wall with concrete-filled steel tubular (CFST) column elements was proposed. An energy dissipation shear wall specimen with CFST column elements (GZSW) and an ordinary reinforced concrete shear wall (SW) were constructed, and experimented by low-cycle reversed loading. The mechanical characteristics of these two specimens, including the bearing capacity, ductility, energy dissipation, and stiffness degradation process, were analyzed. The finite-element model of the GZSW was established by ABAQUS. Based on this finite-element model, the effect of the placement of steel-plate energy dissipation connectors on the seismic performance of the shear wall was analyzed, and optimization was performed. The experiment results prove that, the GZSW exhibited a superior seismic performance in terms of bearing capacity, ductility, energy dissipation, and stiffness degradation, in comparison with the SW. The results calculated by the ABAQUS finite-elements model of GZSW corresponded well with the results of experiment, and it proved the rationality of the established finite-elements model. In addition, the optimal placement of the steel-plate energy dissipation connectors was obtained by ABAQUS.

고정 지연 조건에서 전력-지연 효율성의 최적화를 위한 논리 경로 설계 (On a Logical Path Design for Optimizing Power-delay under a Fixed-delay Constraint)

  • 이승호;장종권
    • 정보처리학회논문지A
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    • 제17A권1호
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    • pp.27-32
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    • 2010
  • Logical Effort의 기법은 회로의 지연 값을 간단한 필산으로 신속하게 측정할 수 있는 기술이다. 이 기법은 설계 공정 시간을 절약하는 장점도 있지만 고정 지연이라는 설계조건에서 회로의 면적이나 전력의 최소화를 도출할 수 있는 논리 경로를 설계하는데 약점도 있다. 이 논문에서는 균형 지연 모형을 제안하고 이 방법을 기반으로 논리경로에서 전력-지연 효율성을 최적화하는 기법을 제안하고자 한다. 본 논문의 기법을 사용하여 8-input AND 게이트의 3가지 서로 다른 설계 회로를 모의 시험한 결과 기존 Logical Effort의 기법보다 약 40%정도 전력 소비의 효율성이 향상되었다.