• Title/Summary/Keyword: Effective capacitance

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Electroporation Conditions for DNA Transfer into Somatic Embryogenic Cells of Zoysia japonica (들잔디 체세포 배발생 세포로의 DNA 전입을 위한 Electroporation 조건 구명)

  • 박건환;안병준
    • Korean Journal of Plant Tissue Culture
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    • v.25 no.1
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    • pp.13-19
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    • 1998
  • We have reported previously that intact embryogenic cells can be used instead of protoplasts for electroporation-mediated transformation of zoysiagrass and rice. In this study, conditions of the tissue electroporation were examined to optimize the procedures. Embryogenic cell suspensions were established in liquid MS medium containing 2 mg/L of 2,4-D with embryogenic calluses induced from mature embryos of Z. japonica. The suspension-cultured cell clumps were electroporated with 35S-gusA expression vector DNA, and degrees of DNA introduction into the cells were determined by histological expression rates of the gusA marker gene. DNA transfer into the cell clumps occurred in wide range of voltage (100-400 V) and capacitance (10-1980 $\mu\textrm{F}$), but more in the ranges of 200-300 V and 330-800 $\mu\textrm{F}$ DNA concentrations higher than 6 $\mu\textrm{g}$/mL were adequate for GUS expression of the electroporated cells. DNA transfers were confirmed in all three embryogenic cell lines but only in one out of eleven non-embryogenic lines. Positive GUS expressions occurred with DNAs added even 20-40 h after pulse treatments. As a promoter of gusA, Act1 and Ubi1 were effective 7 and 5 times than 35S respectively in number of GUS expression units on electroporated cell clumps. Embryogenic cell clumps survived and regenerated into plantlets after pulse treatments of wide range of conditions.

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Quantum Effects in the channel of a ${\delta}$ - doped NMOSFET (${\delta}$ - 도핑 NMOSFET 채널 내에서의 양자화 효과)

  • 문현기;김현중;이찬호
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.177-180
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    • 2001
  • The quantum effects in the channel of a $\delta$ -doped NMOSFET structures are investigated by solving Schrodinger and Poisson equations self-consistently. According to the scaling of MOSFET structures, electron distributions change by the strong energy quantization. However the presence of a low-doped epitaxial region produces a reduction of the electron effective field for a given charge sheet density and therefore, improves the electron effective mobility. We also focus the quantum-induced threshold voltage shifts, low-field electron effective mobility and gate-to-channel capacitance. The reported results give indications for the fabrication of ultra short MOSFET's.

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Shielding effect model and Signal Switching in the multi-layer interconnects (다층 배선에서 차폐효과 모델 및 스위칭에 미치는 영향)

  • 진우진;어영선
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1145-1148
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    • 1998
  • New capacitance modeling and transient analysis for multi-layer interconnects with shielding effect are presented. The upper layer capacitances with under-layer shielding lines are represented by introducing a filling factor η which can be defined as the ratio of upper-layer line length to the total under-layer line width. The upper-layer effective self capacitances considering two extreme cases which the underlayer metals are assumed as a ground or as a Vdd are modeled. The signal transient analysis with shielding effect model is performed.

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Effect of Heat Treatments on Tungsten Polycide Gate Structures (텅스텐 폴리사이드 게이트 구조에서의 열처리 효과)

  • 고재석;천희곤;조동율;구경완;홍봉식
    • Journal of the Korean Vacuum Society
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    • v.1 no.3
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    • pp.376-381
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    • 1992
  • Tungsten silicide films were deposited on the highly phosphorus-doped poly Si/SiO2/Si substrates by Low Pressure Chemical Vapor Deposition. They were heat treated in different conditions. XTEM, SIMS and high frequency C-V analysis were conducted for characterization. It can be concluded that outdiffusion of phosphours impurity throught the silicide films lead to its depletion in the poly-Si gate region near the gate oxide, resulting in loss of capacitance and increase of effective gate oxide thickness.

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Parameter extraction and signal transient of IC interconnects on silicon substrate (실리콘기판 효과를 고려한 전송선 파라미터 추출 및 신호 천이)

  • 유한종;어영선
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.871-874
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    • 1998
  • A new transmission line parameter extraction method of iC interconnects on silicon substrate is presented. To extract the acurate parameters, the silicon substrate effects were taken into account. Since the electromagnetic fields under the silicon substrate are propagated with slow wave mode, effective dielectric constant and different ground plane with the multi-layer dielectric structures were employed for inductance and capacitance matrix determination. Then accurate signal transients simulation were performed with HSPICE by using the parameters. It was shown that the simulation resutls has an excellent agreement with TDR/TDT measurements.

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A Simple and Size-effective design method of Battery Charger with Low Ripple Current (작은 전류리플을 갖는 저면적 배터리 충전회로 설계)

  • Chung, Jin-Il;Kwack, Kae-Dal
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.523-524
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    • 2008
  • Proposed battery charger is a economic candidate because that is simple and small size. The circuit has linearly operational power stage. That use small size buffer with small driving current and large power MOS gate capacitance. The simulation result show that charging current is stable and has low ripple.

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Mesh Patterned High Tunable MIM Capacitor

  • Lee, Young-Chul
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.640-643
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    • 2008
  • In this work, a novel tunable MIM capacitor with the meshed electrode is proposed first in order to improve the tunability characteristics using fringe fields. The capacitors were fabricated on a low-resistivity Si substrate employing lead zinc niobate (PZN) thin film dielectric. The fabricated capacitor with the meshed electrode, whose line width and spacing was $2.5{\mu}m$, achieved the effective capacitance tunability of 31 % that is higher value of 18.5 % than that of the conventional capacitor with the rectangular-type electrode.

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Electrical properties of multilayer piezoelectric actuator with the variations of temperature (적층 압전액츄억이터 소자의 온도해 따른 전기적 특성)

  • Lee, Kab-Soo;Lee, Il-Ha;Yoo, Ju-Hyun
    • Proceedings of the KIEE Conference
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    • 2006.10a
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    • pp.63-64
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    • 2006
  • In this paper, multilayer piezoelectric actuator was fabricated in order to develop ultrasonic linear motor. Multilayer actuator showed a high density of 7.78[$g/cm^3$], a large effective electromechanical coupling factor($K_{eff}$) of 0.259, a high mechanical quality factor( Qm ') of 1301, and high capacitance(c) of 19.32[nF]. Curie temperature was $343[^{\circ}C]$.

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Li-doped p-type ZnS Grown by Molecular Beam Epitaxy

  • Lee Sang-Tae
    • Journal of Advanced Marine Engineering and Technology
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    • v.29 no.3
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    • pp.313-318
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    • 2005
  • Li-doped ZnS layers were grown by molecular beam epitaxy. It was found that relatively low growth temperature is suitable for effective incorporation of Li acceptors. The layers grown under optimized conditions exhibited photoluminescence spectra dominated by neutral-acceptor-bound excitons. Such layers also showed electrically p-type behavior in capacitance-voltage characteristics. The net acceptor concentration is estimated to be approximately $3{\times}10^{15}\;cm^{-3}$.

Design and Fabrication of An Improved Capacitor Multiplier with Good Frequency Characteristics (주파수 특성이 향상된 커패시터 멀티플라이어 설계 및 제작)

  • Lee, Dae-Hwan;Back, Ki-Ju;Han, Da-In;Ryu, Byoung-Son;Kim, Yeong-Seuk
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.4
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    • pp.59-64
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    • 2013
  • In this paper, a capacitor multiplier with good frequency characteristics has been proposed. Effective capacitance of conventional capacitor multiplier decreases as frequency increases due to internal series resistance. On the other hand, the proposed capacitor multiplier using cascode structure has smaller internal resistance, thus shows good frequency characteristics. Conventional and proposed capacitor multiplier were fabricated using Samsung $0.13{\mu}m$ CMOS process and frequency characteristics of capacitor multipliers were measured using LPF. Measurement results show that the conventional capacitor multiplier has maximum 53% of capacitance error, however the proposed multiplier has less than 10% of capacitance error for the frequency change from 100kHz to 1MHz.