• Journal of Electrical Engineering and Technology
• /
• 제6권2호
• /
• pp.233-238
• /
• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1992년도 하계학술대회 논문집 B
• /
• pp.809-812
• /
• 1992

Charateristics of the ECR etch were Investigated about $MoSi_2$ layer which is widely used for the capping layer and barrier layer in VLSI metallization. The etch rate was evaluated according to gas ratio of $SF_6/BCl_3$, $N_2$ flow rate, RF power and chamber pressure. The chamber pressure, the most important factor, represented the maximum etch rate at about the pressure of 10 mTorr.

• 한국정밀공학회지
• /
• 제21권4호
• /
• pp.32-38
• /
• 2004

Laser-induced thermochemical wet etching of titanium in phosphoric acid has been investigated to examine the feasibility of this method fur fabrication of microstructures. Cutting, drilling, and milling of titanium foil were carried out while examining the influence of process parameters on etch width, etch depth, and edge straightness. Laser power, scanning speed of workpiece, and etchant concentration were chosen as major process parameters influencing on temperature distribution and reaction rate. Etch width increased almost linearly with laser power showing little dependence on scanning speed while etch depth showed wide variation with both laser power and scanning speed. A well-defined etch profile with good surface quality was obtained at high concentration condition. Fabrication of a hole, micro cantilever beam, and rectangular slot with dimension of tess than 100${\mu}{\textrm}{m}$ has been demonstrated.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
• /
• pp.770-772
• /
• 1998

The highest etch rate of Pt film was obtained at 10% $Cl_2$/90% Ar gas mixing ratio in our previous investigation. However, the problems such as the etch residues(fence) remained on the pattern sidewall, low selectivity to oxide as mask and low etch slope were presented. In this paper, the etching by additive $O_2$ gas to 10% $Cl_2$/90% Ar gas base was examined. As a result, the fence-free pattern and high etch slope was observed and the selectivity to oxide increased without decreasing of the etch rate. And the reasons for this phenomenon was investigated by XPS(x-ray photoelectron spectroscopy) surface analysis and plasma characteristic.

• 한국결정성장학회지
• /
• 제11권3호
• /
• pp.102-105
• /
• 2001

A parametric cmpariosn of etch rate and etch selectivity has been performed for GaN, InN and AIN etched in chlorine- and boron halides-based Inductively Coupled Plasma (ICP) discharges. Chlorine-based chemistries produced controllable etch rates (50~150 nm/min) and maximum etch selectivities ~6 for InN over GaN and ~10 for InN over AlN. Maximum etch selectivities of ~100 for InN over GaN and InN over AlN were obtained in boron halides-based discharges and smooth etched surface morphologies were also achieved.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
• /
• pp.1272-1275
• /
• 2008

We present the development of dry etch process for the liquid crystal display (LCD) fabrication using a dielectric barrier discharge (DBD) system at atmospheric pressure. In this experimental work, the dry etch characteristics and the electrical properties of thin film transistor are evaluated by using the scanning electron microscopy and electric probe, and TFT-LCD panel ($300\;mm\;{\times}\;400\;mm$) is manufactured with the application of the amorphous silicon etch step in the 4 mask and 5 mask processes.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 하계학술대회 논문집
• /
• pp.175-175
• /
• 2010

The etching characteristics with etch rate of ITO thin films in an $O_2/BCl_3$/Ar plasma were investigated. The etch rate of ITO thin films increased with increasing $O_2$ content from 0 to 10 % in $BCl_3$/Ar plasma, whereas that of ITO decreased with increasing $O_2$ content from 10 % to 30 % in $BCl_3$/Ar plasma. The maximum etch rate of 65.9 nm/min for the ITO thin films was obtained at 10 % $O_2$ addition. The etch conditions were the RF power of 500 W, bias power of 200 W, and process pressure of 2 Pa. The analysis of x-ray photoelectron spectroscopy (XPS) was carried out to investigate the chemical reactions between the surfaces of ITO thin films and etch species.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 추계학술대회 논문집
• /
• pp.583-586
• /
• 2000

The non-selective method by polishing after grinding was used widely to thinning of SDB SOI structures. This method was very difficult to thickness control of thin film, and it was dependent on equipments. However electrochemical etch-stop, one of the selective methods, was able to accurately thickness control and etch equipment was very simple. Therefore, this paper described with the effect of leakage current and electrodes on electrochemical etch-stop. Consequentially, PP(passivation potential) was changed according to the kinds of contact and contact sizes, but OCP(open current potential) was not change with range of -1.5~-1.3V

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 추계학술대회 논문집
• /
• pp.579-582
• /
• 2000

This paper described on the fabrication of SOI(Si-on-insulator) structures with buried cavities by SDB technology and eletrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annaling(100$0^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated the SDB SOI structure with buried cavities as well as an accurate control and a good flatness.

• 한국전기전자재료학회논문지
• /
• 제24권10호
• /
• pp.779-783
• /
• 2011

The morphology of etch pits in commercial 4H-SiC epi-wafer were investigated by molten-KOH etching. The etching process was optimized in $525{\sim}570^{\circ}C$ at 2~10 min and the novel type of etch pits was revealed. This type of etch pits have been considered as TED (threading edge dislocation) II, its origin and nature, however, are not reported yet. In this work, the morphology and evolution of etch pits during epitaxial growth were analyzed and the different behavior between TED and TEDII was discussed.