• 전기전자학회논문지
• /
• 제10권2호통권19호
• /
• pp.149-155
• /
• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.

• 한국정보전자통신기술학회논문지
• /
• 제12권2호
• /
• pp.150-154
• /
• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• 전기전자학회논문지
• /
• 제11권1호통권20호
• /
• pp.54-60
• /
• 2007

본 연구에서는 고속 I/0 인터페이스용 ESD(Electro-Static Discharge)보호소자로서 SCR(Silicon Controlled Rectifier)구조에 기반한 새로운 구조의 ESD보호소자인 N/P-type Low Voltage Triggered Silicon-Controlled Rectifier(NPLVTSCR)을 제안하였다. 제안된 NPLVTSCR은 기존 SCR이 갖는 높은 트리거 전압($\sim$20V)을 낮추고 ($\sim$5V) 또한 정상상태에서의 보호소자의 래치업 현상을 줄일 수 있다. 본 연구에서 제안된 NPLVTSCR의 전기적 특성 및 ESB감내특성을 확인하기 위하여 TCAD툴을 이용하여 시뮬레이션을 수행하였으며, 또한 TSMC 90nm공정에서 테스트 패턴을 제작하여 측정을 수행하였다. 시뮬레이션 및 측정 결과를 통해, NPLVTSCR은 PMOS 게이트 길이에 따라 3.2V $\sim$ 7.5V의 트리거링 전압과 2.3V $\sim$ 3.2V의 홀딩전압을 갖으며, 약 2kV의 HBM ESD 감내특성을 갖는 것을 확인 할 수 있었다.

• 전기학회논문지
• /
• 제63권2호
• /
• pp.319-324
• /
• 2014

The wafer carrier is made of PP, PC, PE resin which have excellent heat and chemical resistance and electrical properties. However, particle generation has become a problem due to static electricity generated in the carrier. Some conductive material such as carbon black (CB) and carbon fiber (CF) are added for the purpose of anti-static, however, additional for motility and particle contamination problems due to high carbon content occurs. In this paper, the electrical characteristics and workability are observed and compared by adding low Carbon Nono Tube(CNT) to each PP, PC and PE resin to solve the problem.

• 한국전자파학회논문지
• /
• 제24권10호
• /
• pp.979-986
• /
• 2013

본 논문에서는 이동통신 기기에서 ESD(ElectroStatic Discharge) 보호소자로 흔히 사용되는 TVS(Transient Voltage Suppressor) diode로 야기되는 잡음 신호가 안테나 무선감도 저하에 미치는 영향에 대해 분석하였다. 다양한 기능을 가진 스마트폰의 경우, 좁은 실장 공간으로 인해 스피커가 안테나 영역 근처에 존재할 수 있고, 스피커로 유입되는 ESD로부터 오디오 증폭기를 보호하기 위한 TVS가 안테나 GND로 사용되어지는 영역에 위치할 수 있다. 스피커를 구동시키는 class-D 증폭기에서 발생하는 디지털 오디오 신호와 안테나에서 커플링되어 스피커로 전달되어진 CDMA(Code Division Multiple Access) RF(Radio Frequency) 통신 신호가 TVS에 의해 믹싱되고, 안테나의 GND로 누설되어 안테나 무선감도를 저하시키는 현상에 대해 실험적 분석후 시뮬레이션을 통해 검증하였다. 이를 통해 비선형적인 ESD 보호소자가 신호의 원치 않는 결합통로가 되는 문제를 사전에 차단할 수 있을 것으로 보인다.

• Journal of Power Electronics
• /
• 제15권6호
• /
• pp.1673-1681
• /
• 2015

A low dropout (LDO) regulator with a wide-bandwidth is proposed in this paper. The regulator features a Human Body Model (HBM) 8kV-class high robustness ElectroStatic Discharge (ESD) protection circuit, and two error amplifiers (one with low gain and wide bandwidth, and the other with high gain and narrow bandwidth). The dual error amplifiers are located within the feedback loop of the LDO regulator, and they selectively amplify the signal according to its ripples. The proposed LDO regulator is more efficient in its regulation process because of its selective amplification according to frequency and bandwidth. Furthermore, the proposed regulator has the same gain as a conventional LDO at 62 dB with a 130 kHz-wide bandwidth, which is approximately 3.5 times that of a conventional LDO. The proposed device presents a fast response with improved load and line regulation characteristics. In addition, to prevent an increase in the area of the circuit, a body-driven fabrication technique was used for the error amplifier and the pass transistor. The proposed LDO regulator has an input voltage range of 2.5 V to 4.5 V, and it provides a load current of 100 mA in an output voltage range of 1.2 V to 4.1 V. In addition, to prevent damage in the Integrated Circuit (IC) as a result of static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class (Chip level) ESD protection circuit of a P-substrate-Triggered Silicon Controlled Rectifier (PTSCR) type with high robustness characteristics.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
• /
• pp.1593-1594
• /
• 2006

본 논문에서는 모바일 컨버젼스 단말기를 위한 Tunable Image Rejection Filter를 구현 하였다. 이 필터는 TSMC 0.25um 공정을 이용해 시뮬레이션 되었다. 또한 정전기로 인한 소자의 파괴를 방지하기 위해 ESD 패드(Electro Static Discharge Pad)를 추가하였다. 영상 주파수 저지 특성은 WCDMA(2.1GHz), WiBro(2.3GHz), WLAN(2.45) 대역에서 모두 28dB 이상이고, 이때 바이어스 전압은 각각 0.5V, 0.95v, 1.8V의 전압을 가지게 되었다. 삽입 손실은 세 대역에서 모두 2dB 이하이다.

• 마이크로전자및패키징학회지
• /
• 제11권1호
• /
• pp.43-47
• /
• 2004

We have been using Moisture Barrier Bags for dry packing of semiconductor packages to prevent moisture from absorbing during shipping. Moisture barrier bag material is required to be waterproof, vapor proof and offer superior ESD (Electro-static discharge) and EMI shielding. Also, the bag should be formed easily to the shape of products for vacuum packing while providing excellent puncture resistance and offer very low gas ＆ moisture permeation. There are some problems like pinholes and punctured bags after sealing and before the surface mount process. This failure may easily result in package pop corn crack during board mounting. The bags should be developed to meet the requirements of excellent electrical and physical properties by means of optimization of their raw material composition and their thickness. This study investigates the performance of moisture barrier bags by characterization of their mechanical endurance, tensile strength and through thermal analysis. By this study, we arrived at a robust material composition (polyester/Aluminate) for better packing.