• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.167-170
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• 2021

현재, 주요 선진국들을 포함하여 Google과 IBM과 같은 국제 대기업들을 필두로 양자 컴퓨터 개발에 전폭적인 투자들을 하고 있다. 양자 컴퓨터는 특정 분야에 있어 월등한 계산 능력을 보여주며, 기존 컴퓨터에서는 해결할 수 없던 몇몇 문제들을 빠른 시간 내에 해결한다. 이러한 양자 컴퓨터의 등장은 기존 컴퓨터에서는 사실상 풀 수 없는 암호 알고리즘들을 빠른 시간 내에 해결하여 암호학계에 큰 위협이 되고 있다. 현재 사용하고 있는 대부분의 공개키 암호 알고리즘인 RSA와 ECC(Elliptic Curve Cryptography) 또한 공격 대상이다. NIST에서는 다가오는 양자 컴퓨터 시대에 대비하여 양자내성암호 공모전을 주최하였으며 현재 라운드 3에 도입하였다. 본 논문에서는 라운드 3의 후보 알고리즘인 코드기반암호를 공격하는 ISD(Information Set Decoding) 알고리즘에 관한 동향을 조사하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.1-8
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• 2007

In wireless sensor network which uses limited battery, power consumption is very important factor for the survivality of the system. By using low-power communication to reduce power consumption, error rate is increased in typical conditions. This paper analyzes power consumption of specific error control coding (ECC) implementations. With identical link quality, ECC provides coding gain which save the power for transmission at the cost of computing power. In sensor node, transmit power is higher than computing power of Micro Controller Unit (MCU). In this paper, Viterbi algerian is applied to the low-transmit-power sensor networks in terms of network power consumption. Practically, Viterbi algorithm presents 20% of reduction of re-transmission in compared with Auto Repeat Request (ARQ) system. Furthermore, it is observed that network power consumption is decreased by almost 18%.

• Journal of KIISE:Software and Applications
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• v.32 no.9
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• pp.847-852
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• 2005

Over the last decade, numerous complexity measurement techniques for Object-Oriented (OO) software system have been proposed for managing the effects of OO codes. These techniques may be based on source code analysis such as WMC (Weighted Methods per Class) and LCOM (Lack of Cohesion in Methods). The techniques are limited to count the number of functions (C++). However. we suggested a new weighted method that checks the number of parameters, the return value and its data type. Then we addressed an effective complexity measurement technique based on the weight of class interfaces to provide guidelines for measuring the class complexity of OO codes in reverse engineering. The results of this research show that the proposed complexity measurement technique ECC(Enhanced Class Complexity) is consistent and accurate in C++ environment.

• Convergence Security Journal
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• v.23 no.1
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• pp.45-54
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• 2023

Recently, with the development of the Internet of Things, research on protocols that can easily connect devices without a UI to the network has been steadily conducted. To this end, the Wi-Fi Alliance announced Wi-Fi Easy Connect, which can connect to a network using a QR code. However, since Wi-Fi Easy Connect requires a large amount of computation for safety, it is difficult to apply to low-power and miniaturized IoT devices. In addition, Wi-Fi Easy Connect considering scalability is designed to operate in a wired environment, but problems such as duplicate encryption occur because it does not consider a security environment like TLS. Therefore, in this paper, we analyze the Wi-Fi Easy Connect protocol and propose a protocol that can operate efficiently in the TLS environment. It was confirmed that the proposed protocol satisfies the existing security requirements and at the same time reduces about 67% of ECC scalar multiplication operations with a large amount of computation.

• Journal of IKEEE
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• v.28 no.1
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• pp.116-122
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• 2024

AMBA AHB-Lite bus is widely used in on-chip bus protocol for low-power and cost-effective SoC. However, it lacks built-in error detection and correction for end-to-end data integrity. This can lead to data corruption and system instability, particularly in harsh environments like automotive applications. To mitigate this problem, this paper proposes the application of SEC-DED (Single Error Correction-Double Error Detection) to AMBA AHB-Lite bus. It aims not only to detect errors in real-time but also to correct them, thereby enhancing end-to-end data integrity. Simulation results demonstrate real-time error detection and correction when errors occur, which bolsters end-to-end data integrity of automotive on-chip bus.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.633-637
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• 2005

In this contribution, we developed and improved an existing GF (Galois field) dividing algorithm by suggesting a novel architecture for a finite field divider, which is frequently required for the error correction applications and the security-related applications such as the Reed-Solomon code, elliptic curve encryption/ decryption, is proposed. We utilized the VHDL language to verify the design methodology, and implemented the architecture on an FPGA chip. We suggested the n-bit lookup table method to obtain the throughput of 2m/n cycles, where m is the order of the division polynomial and n is the number of the most significant lookup-bits. By doing this, we extracted the advantages in achieving both high-throughput and less cost of the gate areaon the chip. A pilot FPGA chip was implemented with the case of m=4, n=2. We successfully utilized the Altera's EP20K30ETC144-1 to exhibit the maximum operating clock frequency of 77 MHz.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.4
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• pp.287-295
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• 1986

In this paper, a SBC(sub-band-coding) is proposed to code a speech signal for a digital mobile radio and a robustness of speech quality of the SBC over the Rayleigh fading channel is investigated via a computer simulation. First the Rayleigh fading channel and 16-ary DPSK receiver models are presentes and verified its validitties by comparing with theoretical values. Three different measures: SNR, LPC distance measure and subjective listening test, were used to evaluate the effects due to the Rayleigh fading channel errors. From the results of computer simulation at BER=$10_{-3}$, $10_{-2}$, 5$ imes$$10_{-2}$, it was found that the speech remained quite intelligible at BER=$10_{-2}$and the link is still usuable even at BER=5$ imes$$10_{-2}$ Thus it was concluded that the SBC can be applicable to the digital mobile radio on the Rayleigh fading channel error in the range of $10_{-4}$~$10_{-2}$ without emplowing any error correction codes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.6
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• pp.540-549
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• 2013

An adaptive non-uniform quantization scheme is proposed for soft-decision error correction in NAND flash memory. Even though the conventional maximizing mutual information (MMI) quantizer shows the optimal post-FEC (forward error correction) bit error rate (BER) performance, this quantization scheme demands heavy computational overheads due to the exhaustive search to find the optimal parameter values. The proposed quantization scheme has a simple structure that is constructed by only six parameters, and the optimal values of them are found by maximizing the mutual information between the input and the output symbols. It is demonstrated that the proposed quantization scheme improves the BER performance of soft-decision decoding with only small computational overheads.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.907-910
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• 2009

This paper is the FPGA Implementation of Reed-Solomon Encoder that is one of Error control Codes. Reed-Solomon codes are block-based error control codes with a wide range of applications in digital communications. RS codes are strong on burst errors because it process signals as symbol. We simulate this system using Matlab from Mathworks and design it using System Generator from Xilinx. We refer Matlab source in Implementation of Reed-Solomon Error Control Coding for Compressed Images by Simon Anthony Raspa.