The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Adaptive Quantization Scheme for Multi-Level Cell NAND Flash Memory

멀티 레벨 셀 낸드 플래시 메모리용 적응적 양자화기 설계

  • 이동환 (서울대학교 전기 정보 공학부 멀티미디어 시스템 연구실) ;
  • 성원용 (서울대학교 전기 정보 공학부 멀티미디어 시스템 연구실)
  • Received : 2013.04.01
  • Accepted : 2013.06.05
  • Published : 2013.06.30
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Abstract

An adaptive non-uniform quantization scheme is proposed for soft-decision error correction in NAND flash memory. Even though the conventional maximizing mutual information (MMI) quantizer shows the optimal post-FEC (forward error correction) bit error rate (BER) performance, this quantization scheme demands heavy computational overheads due to the exhaustive search to find the optimal parameter values. The proposed quantization scheme has a simple structure that is constructed by only six parameters, and the optimal values of them are found by maximizing the mutual information between the input and the output symbols. It is demonstrated that the proposed quantization scheme improves the BER performance of soft-decision decoding with only small computational overheads.

본 논문에서는 멀티 레벨 셀 낸드 플래시 메모리에서 연판정 에러 정정을 위한 적응적 비균일 양자화기를 제안한다. 기존의 최대 상호 정보(maximum mutual information) 양자화기는 최적의 연판정 에러 정정 성능을 보이지만, 소모적인 탐색(exhaustive search)으로 인하여 많은 계산량을 요구한다. 본 논문에서 제안된 양자화기는 최대 여섯 개의 파라미터로 표현되는 간단한 구조를 갖고 있어 연산량이 적다. 또한 제안된 양자화기는 쓰기 심볼과 읽기 심볼 사이의 상호 정보를 최대화하는 방향으로 파라미터 값의 최적화시키므로, 최대 상호 정보 양자화기에 근접하는 우수한 연판정 에러 정정 성능을 보인다.

Keywords

References

  1. W. Liu, J. Rho, and W. Sung, "Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories," in Proc. IEEE Workshop Signal Process. Syst. Design Implementation (SIPS), pp. 303-308, Banff, Canada, Oct. 2006.
  2. B. Chen, X. Zhang, and Z. Wang, "Error correction for multi-level NAND flash memory using Reed-Solomon codes," in Proc. IEEE Workshop Signal Process. Syst. (SiPS), pp. 94-99, Washington D.C., U.S.A., Oct. 2008.
  3. G. Dong, N. Xie, and T. Zhang, "On the use of soft-decision error correction codes in NAND flash memory," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 2, pp. 429-439, Feb. 2011. https://doi.org/10.1109/TCSI.2010.2071990
  4. C. Yang, Y. Emre, and C. Chakrabarti, "Product code schemes for error correction in MLC NAND flash memories," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 12, pp. 2302-2314, Dec. 2012. https://doi.org/10.1109/TVLSI.2011.2174389
  5. J. Wang, T. Courtade, H. Shankar, and R. Wesel, "Soft information for LDPC decoding in flash: Mutual-information optimized quantization," in Proc. IEEE Global Commun. Conf. (GLOBECOM 2011), pp. 1-6, Houston, U.S.A., Dec. 2011.
  6. D. Lee and W. Sung, "Estimation of NAND flash memory threshold voltage distribution for optimum soft-decision error correction," IEEE Trans. Signal Process., vol. 61, no. 2, pp. 440-449, Jan. 2013. https://doi.org/10.1109/TSP.2012.2222399
  7. J. Cho, J. Kim, and W. Sung, "Optimal output quantization of binary input AWGN channel for belief-propagation decoding of LDPC codes," in Proc. IEEE Workshop on Signal Process. Syst. (SiPS), pp. 282-287, Quebec City, Canada, Oct. 2012.
  8. J. Kim, D. Lee, and W. Sung, "Performance of rate 0.96 (68254, 65536) EG-LDPC code for NAND flash memory error correction," in Proc. IEEE Int. Conf. Commun. (ICC), pp. 7029-7033, Ottawa, Canada, June 2012.
  9. G. Dong, Y. Pan, N. Xie, C. Varanasi, and T. Zhang, "Estimating information-theoretical NAND flash memory storage capacity and its implication to memory system design space exploration," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 9, pp. 1705-1714, Sep. 2012. https://doi.org/10.1109/TVLSI.2011.2160747
  10. D. Lee and W. Sung, "Monte Carlo simulation of NAND flash memory channel in the presence of cell to cell interference," in Proc. KICS Winter Conf., pp. 407-407, Yongpyoung, Korea, Feb. 2011.
  11. K.-D. Suh B.-H. Suh, Y.-H. Lim, J.-K. Kim, Y.-J. Choi, Y.-N. Koh, S.-S. Lee, S.-C. Kwon, B.-S. Choi, J.-S. Yum, J.-H. Choi, J.-R. Kim, and H.-K. Lim, "A 3.3 V 32 MB NAND flash memory with incremental step pulse programming scheme," IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995. https://doi.org/10.1109/4.475701