• Title/Summary/Keyword: Dynamic voltage converter

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Small-signal Analysis of the Full bridge ZVZCS converter (풀-브릿지 영전압 영전류 컨버터의 소신호 모델링)

  • Choi, Hang-Seok;Cho, B.H.
    • Proceedings of the KIEE Conference
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    • 1999.07f
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    • pp.2518-2521
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    • 1999
  • A Full-bridge zero-voltage zero-current switching (ZVZCS) converter using transformer auxiliary winding is analyzed. A complete small-signal model for the control scheme is developed. The propoed model is accurate up to half the switching frequency. The dynamic characteristics are compared with those of the zero-voltage switching converter and buck converter. Model predictions are confirmed by experimental measurements.

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A study on the design of the A-D converter for analog rebalance loop in INS (관성측정장치의 아날로그 재평형 루프에 따르는 A-D 변환기의 설계에 관한 연구)

  • 안영석;김종웅;이의행
    • 제어로봇시스템학회:학술대회논문집
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    • 1987.10b
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    • pp.522-527
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    • 1987
  • This paper describes the hardware of analog-to-digital converter to process the rate output of analog servo loop for the gyro rebalance of INS. The analog-to-digital converter is designed by voltage-to-frequency method which is generally used in INS, and this scheme fits well into the strapdown INS that requires the wide dynamic range and linearity. The output of the designed voltage to frequency converter is tested by computer through the counter and all the factors which affect the performance are considered.

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Controller Optimization Algorithm for a 12-pulse Voltage Source Converter based HVDC System

  • Agarwal, Ruchi;Singh, Sanjeev
    • Journal of Electrical Engineering and Technology
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    • v.12 no.2
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    • pp.643-653
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    • 2017
  • The paper presents controller optimization algorithm for a 12-pulse voltage source converter (VSC) based high voltage direct current (HVDC) system. To get an optimum algorithm, three methods namely conventional-Zeigler-Nichols, linear-golden section search (GSS) and stochastic-particle swarm optimization (PSO) are applied to control of 12 pulse VSC based HVDC system and simulation results are presented to show the best among the three. The performance results are obtained under various dynamic conditions such as load perturbation, non-linear load condition, and voltage sag, tapped load fault at points-of-common coupling (PCC) and single-line-to ground (SLG) fault at input AC mains. The conventional GSS and PSO algorithm are modified to enhance their performances under dynamic conditions. The results of this study show that modified particle swarm optimization provides the best results in terms of quick response to the dynamic conditions as compared to other optimization methods.

The Parallel Operation of ZVT-Full Bridge Converter with Dynamic Current Shared Inductor (동적 전류분담 인덕터를 이용한 ZVT 풀 브리지 컨버터의 병렬 운전)

  • Kim, Yong
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.16 no.4
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    • pp.15-21
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    • 2002
  • This paper presents parallel operation of ZVT(Zero Voltage Transition) FUll Bridge Converter with Dynamic Current Shared Inductor. In the conventional method, CT(Current Transformer) have been used tn share the load current equally with converters. In this system, at parallel operation of ZVT Full Bridge Converter, dynamic current shared inductor divides the same current of unit converter and ZVT circuit aids to high efficiency. Superiority of the characteristics is verified through the experiment with a 2[㎾], 50[㎑] prototype converter.

Dynamic Analysis and Control Circuit Design of Isolated Double Step-Down DC-DC Converter (절연형 이중 강압 직류-직류 컨버터의 동특성 해석 및 제어회로 설계)

  • Ha, Heonchul;Kim, Hansang;Choi, Byungcho
    • Proceedings of the KIPE Conference
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    • 2015.07a
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    • pp.229-230
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    • 2015
  • This paper presents practical details about control-loop design and dynamic analysis for a voltage-mode controlled isolated double step-down DC-DC converter. Graphical loop gain method is used to design the feedback compensation and analyze the closed-loop performance of isolated double step-down DC-DC converter. The results of the control design and closed-loop analysis are validated by experiments on a prototype converter.

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Fuzzy Controlled ZVS Asymmetrical PWM Full-bridge DC-DC Converter for Constant load High Power Applications

  • Marikkannan., A;Manikandan., B.V
    • Journal of Electrical Engineering and Technology
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    • v.12 no.3
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    • pp.1235-1244
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    • 2017
  • This paper proposes a fuzzy logic controlled new topology of high voltage gain zero voltage switching (ZVS) asymmetrical PWM full-bridge DC-DC boost converter for constant load and high power applications. The APWM full-bridge stage provides high voltage gain and soft-switching characteristics increase the efficiency and reduce the switching losses. Fuzzy logic controller (FLC) improves the performance and dynamic characteristics of the proposed converter. A comparison with a classical proportional-integral (PI) controller demonstrates the high performances of the proposed technique in terms of effective output voltage regulation under different operating conditions. Simulation is done by integrating two different simulation platforms $PSIM^{(R)}$ and $Matlab^{(R)}/Simulink^{(R)}$ by using SimCoupler tool of $PSIM^{(R)}$. Experimental results using 120W load have been provided to validate the results.

A Design of Interleaved DC-DC Buck-boost Converter with Improved Conduction Loss of Switch (스위치 전도 손실을 개선한 인터리브 DC-DC 벅-부스트 컨버터 설계)

  • Lee, Joo-Young;Joo, Hwan-Kyu;Lee, Hyun-Duck;Yang, Yil-Suk;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.14 no.3
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    • pp.250-255
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    • 2010
  • The interleaved power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. The buck-boost converter used to provide the high output voltage and low output voltage for portable applications. Also we used the PWM(Pulse Width Modulation) control method for high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The interleaved PMIC to reduce output ripple. And step-down DC-DC converter in stand-by mode below 1mA is designed with LDO in order to achive high efficiency.

The design of the high efficiency DC-DC Converter with Dynamic Threshold MOS switch (Dynamic Threshold MOS 스위치를 사용한 고효율 DC-DC Converter 설계)

  • Ha, Ka-San;Koo, Yong-Seo;Son, Jung-Man;Kwon, Jong-Ki;Jung, Jun-Mo
    • Journal of IKEEE
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    • v.12 no.3
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    • pp.176-183
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    • 2008
  • The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit as a block. The Saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 95% at 100mA output current. And DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

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Voltage control of three phase rectifier with current-controlled voltage type converter

  • Woo, Myeong-Ho;Jeong, Seung-Gi
    • Proceedings of the KIEE Conference
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    • 1991.11a
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    • pp.207-209
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    • 1991
  • This paper deals with voltage control method of PWM rectifier using current-controlled voltage type converter. A linearized model of the current-controlled rectifier is derived, which is used to examine the effect of controller gains to its dynamic responses. Through the simulation, it is shown that the proposed model is generally valid, which is confirmed by experimental results.

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Sampled-Data Modeling and Dynamic Behavior Analysis of Peak Current-Mode Controlled Flyback Converter with Ramp Compensation

  • Zhou, Shuhan;Zhou, Guohua;Zeng, Shaohuan;Xu, Shungang;Cao, Taiqiang
    • Journal of Power Electronics
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    • v.19 no.1
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    • pp.190-200
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    • 2019
  • The flyback converter, which can be regarded as a nonlinear time-varying system, has complex dynamics and nonlinear behaviors. These phenomena can affect the stability of the converter. To simplify the modeling process and retain the information of the output capacitor branch, a special sampled-data model of a peak current-mode (PCM) controlled flyback converter is established in this paper. Based on this, its dynamic behaviors are analyzed, which provides guidance for designing the circuit parameters of the converter. With the critical stability boundary equation derived by a Jacobian matrix, the stable operation range with a varied output capacitor, proportional coefficient of error the amplifier, input voltage, reference voltage and slope of the compensation ramp of a PCM controlled flyback converter are investigated in detail. Research results show that the duty ratio should be less than 0.5 for a PCM controlled flyback converter without ramp compensation to operate in a stable state. The stability regions in the parameter space between the output capacitor and the proportional coefficient of the error amplifier are enlarged by increasing the input voltage or by decreasing the reference voltage. Furthermore, the ramp compensation also can extend to the stable region. Finally, time-domain simulations and experimental results are presented to verify the theoretical analysis results.