• Transactions of the Korean Society of Mechanical Engineers
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• v.14 no.6
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• pp.1391-1407
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• 1990

In this paper, optimization procedures are presented considering the static and dynamic constraints for laminated composite plate and hybrid laminated composite plate subject to concentrated load on center of the plates. Design variables for this problem are ply angle or ply thickness. Deflection, natural frequency and specific damping capacity are considered as constraints. Using a recursive linear programming method, the nonlinear optimization problems are solved. By introducing the design scaling factor, the number of iterations is reduced significantly. Composite plates could be designed optimally combined with FEM analysis under various conditions. In the optimization procedure, verification for both analysis and design of the laminated composite plates are compared with the results of the others. Various design results are presented for the laminated composite plates and hybrid laminated composite plates.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.328-330
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• 2006

동적 전력 관리 기법을 활용한 프로세서의 등장은 고성능 임베디드 장치들의 저전력 설계에 있어서 큰 영향을 주고 있다 특히, XSCALE과 같은 고성능 프로세서의 소비전력은 동작 클럭의 속도와 비례하여 빠르게 증가하고 있으며, 이를 극복하기 위한 다양한 기법이 제시되었다. 동적 전력 관리 기법은 크게 1) 동적 전압 관리 기법과 동적 프리퀀시 관리 기법으로 구분된다. 동적 프리퀀시 관리 기법을 사용한 프로세서는 필요에 따라 프로세서의 동작 클럭 속도를 변경한다. 이는 전체적인 프로세서 성능의 저하를 수반하게 된다 특히, 주변 장치들의 전력 관리가 동시에 이루어지지 않을 경우에는 시스템의 전체적인 성능에 큰 영향을 끼치게 된다. I/O 장치의 인터럽트는 CPU의 현재 실행을 잠시 멈추고, 인터럽트 처리를 우선적으로 수행하도록 한다. 따라서 CPU가 처리할 수 있는 양보다 많은 인터럽트 발생은 인터럽트 처리 이후에 실제 응용 프로그램들이 동작할 시간을 줄이게 되어 CPU는 살아있으나, 인터럽트 이외의 실제 프로세스 실행을 진행할 수 없는 라이브륵(livelock) 현상이 발생한다. 동적 프리퀀시 스케일링을 사용하는 경우, 프로세서의 동작 속도 저하로 인한 livelock 현상이 발생할 수 있으며 이를 막기 위하여, 인터럽트 처리를 제한하는 기법을 제시한다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.46 no.2
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• pp.159-166
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• 2018

In this study, the internal structural design, dynamic characteristics and load analyses of the small scaled rotor blade required for LCH(Light Civil Helicopter) main rotor wind tunnel test were carried out. The test is performed to evaluate the aerodynamic performance and noise characteristics of the LCH main rotor system. Therefore, the Mach-scale technique was appled to design the small scaled blade to simulate the equivalent aerodynamic characteristics as the full scale rotor system. It is necessary to increase the rotor speed to maintain the same blade tip speed as the full scale blade. In addition, the blade weight, section stiffness, and natural frequency were scaled according to the Mach-type scaling factor(${\lambda}$). For the design of skin, spar, torsion box, which are the main components of the blade, carbon and glass fiber composite materials were adopted, and composite materials are prepreg types that can be supplied domestically. The KSec2D program was used to evaluate the section stiffness of the blade. Also, structural loads and dynamic characteristics of the Mach scale blade were investigated through the comprehensive rotorcraft analysis program CAMRADII.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.135-140
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• 2020

Recently, due to the rapid diffusion of intelligent systems and IoT technologies, power saving techniques in real-time embedded systems has become important. In this paper, we propose P-GA (Parallel Genetic Algorithm), a scheduling algorithm aims at reducing the power consumption of real-time systems in multi-core hybrid memory environments. P-GA improves the Proportional-Fairness (PF) algorithm devised for multi-core environments by combining the dynamic voltage/frequency scaling of the processor with the nonvolatile memory technologies. Specifically, P-GA applies genetic algorithms for optimizing the voltage and frequency modes of processors and the memory types, thereby minimizing the power consumptions of the task set. Simulation experiments show that the power consumption of P-GA is reduced by 2.85 times compared to the conventional schemes.

• Journal of the Korean Geotechnical Society
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• v.20 no.9
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• pp.91-103
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• 2004

A series of shaking table model tests were performed to verify the validity of similitude law, which is suggested by lai (1989) to simulate the dynamic behavior of soil-fluid-structure system for is shaking table tests. In the tests, the similitude law suggested by lai was applied to determine the length and the time scaling factors. Also, the steady state concept was used in determining the density of model backfill soil, which is a key factor in simulating the development of excess pore pressure during shaking. The similitude law was verified by checking whether three different sizes of quay walls show the identical behavior or not. The similar responses of acceleration, excess pore pressure and horizontal displacement of walls were obtained far the small and large models. However, the medium model showed larger responses than those of the small and large models because of the resonance between the frequency of input acceleration and the natural frequency of the wall system. In addition, the vertical displacement and rotational angle of the walls became larger with the increase of model size.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.367-376
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• 2007

In this paper, we introduce an application-specific and adaptive power management technique for portable systems that support dynamic voltage scaling (DVS). We exploit both the idle time of multitasking systems running soft real-time tasks as well as memory- or CPU-bound code regions. Detailed power and execution time profiles guide an adaptive power manager (APM) that is linked to the operating system. A post-pass optimizer marks candidate regions for DVS by inserting calls to the APM. At runtime, the APM monitors the CPU's performance counters to dynamically determine the affinity of the each marked region. for each region, the APM computes the optimal voltage and frequency setting in terms of energy consumption and switches the CPU to that setting during the execution of the region. Idle time is exploited by monitoring system idle time and switching to the energy-wise most economical setting without prolonging execution. We show that our method is most effective for periodic workloads such as video or audio decoding. We have implemented our method in a multitasking operating system (Microsoft Windows CE) running on an Intel XScale-processor. We achieved up to 9% of total system power savings over the standard power management policy that puts the CPU in a low Power mode during idle periods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.4 s.304
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• pp.167-176
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• 2005

This paper proposes a new power minimization technique for the frame-based multimedia signal processing. The derivation of the technique is based on the newly proposed microscopic DVS(Dynamic Voltage Scaling) method, where, the operating frequency and the supply voltage levels are dynamically controlled according to the processing requirement for each frame of multimedia data. The multimedia signal processing algorithms are also redesigned and optimized to maximize the power saving efficiency of the microscopic DVS technology. The characterization of the mean/variance distribution of the processing load in the frame-based multimedia signal processing provides the major basis not only for the optimized application of the microscopic DVS technology but also for the optimization of the multimedia algorithms. The power saying efficiency of the proposed DVS approach is experimentally tested with the algorithms of MPEG-2 video decoder and MPEG-2 AAC audio encoder on the ARM9 RISC processor. The experimental results with the diverse MPEG-2 video and audio files show The average power saving efficiencies of 50$\%$ and 30$\%$, respectively. The results also agree very well with those of the analytic derivations.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.517-526
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• 2008

As the functionality of portable devices arc being enhanced and the performance is being greatly improved, power dissipations of battery driven portable devices are being increased. So, an efficient power management for reducing their power consumption is needed. In this paper, we propose a window-based DVS algorithm for MPEG Player. The proposed algorithm maintains the recently frame information and execution time received from MPEG player in window queue and dynamically adjusts (frequency, voltage) level based on window queue information. Our algorithm can be implemented in the common multimedia player as a module. We employed well-known MPlayer for the measurement of performance. The experimental result shows that the proposed algorithm reduces energy consumption by 56% on maximal performance.

• International Journal of Automotive Technology
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• v.4 no.4
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• pp.181-191
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• 2003

Since the nonlinearity and uncertainties which inherently exist in vehicle system need to be considered in active suspension control law design, this paper proposes a new control strategy for active vehicle suspension systems by using a combined control scheme, i.e., respectively using a genetic algorithm (GA) based self-tuning PID controller and a fuzzy logic controller in two loops. In the control scheme, the PID controller is used to minimize vehicle body vertical acceleration, the fuzzy logic controller is to minimize pitch acceleration and meanwhile to attenuate vehicle body vertical acceleration further by tuning weighting factors. In order to improve the adaptability to the changes of plant parameters, based on the defined objectives, a genetic algorithm is introduced to tune the parameters of PID controller, the scaling factors, the gain values and the membership functions of fuzzy logic controller on-line. Taking a four degree-of-freedom nonlinear vehicle model as example, the proposed control scheme is applied and the simulations are carried out in different road disturbance input conditions. Simulation results show that the present control scheme is very effective in reducing peak values of vehicle body accelerations, especially within the most sensitive frequency range of human response, and in attenuating the excessive dynamic tire load to enhance road holding performance. The stability and adaptability are also showed even when the system is subject to severe road conditions, such as a pothole, an obstacle or a step input. Compared with conventional passive suspensions and the active vehicle suspension systems by using, e.g., linear fuzzy logic control, the combined PID and fuzzy control without parameters self-tuning, the new proposed control system with GA-based self-learning ability can improve vehicle ride comfort performance significantly and offer better system robustness.