• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.391-393
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• 2002

DSTM 기술은 IPv6 네트워크가 도입되기 시작함에 따라 논의되어야 할 가장 중요한 이슈들 중 하나로서 기존의 IPv4 에서 IPv6 로의 자연스러운 이전을 지원해 주는 IPv6 트랜지션 기술 중 하나이다. 이 기술은 IPv6 망에서 dual stack 을 기본으로 채택하여 해당IPv6 호스트의 IPv4 응용을 수정하지 않고 IPv6 터널링(Tunneling) 기술을 채택하여 목적지 IPv4 응용과의 통신을 제공한다. 본 논문은 이러한 DSTM 요소 기술 중 하나인 IPv6 호스트에 동적으로 IPv4 주소를 할당, 해제 및 IPv6 터널링을 관리 하는 DSTM Server와Client의 설계 및 구현을 기술한다.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2003.05a
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• pp.1004-1008
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• 2003

Near-filed optical storage using cantilever aperture tip is a promising way fer next generation optical data storage. To enhance the speed of reading and writing data, gap between tip and media should be controlled fast and precisely within near field region. In this paper, several PZT actuators are analyzed far constructing dual servo control algorithm: coarse actuators(stact. PZT, bimorph PZI) for media surface inclination and One actuator(film PZT) for media surface roughness. Dynamic analysis of stack PZT, bimorph PZT, and film PZT are performed through the frequency response. Based on the frequency response and mathematical model, fast analog controller is designed.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1257-1260
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• 2002

3 세대 이동통신 시스템인 UMTS/GPRS 는 모든 MS(Mobile Station)에게 인터넷 서비스를 항상 제공할 수 있도록 하는 것을 목표로 하고 있다. 그러나 최근 인터넷 사용의 증가로 인해 public IPv4 주소 부족 현상이 발생함에 따라 인터넷에 연결되어 있는 모든 MS 에게 public IPv4 주소를 할당하는데 한계가 있다. 이에 따라 3GPP의 Release 2000 IM CN(IP Multimedia Core Network) 서브 시스템에서는 멀티미디어 서비스 지원을 위해 인터넷에 연결되어 있는 모든 MS 에게 IP 를 할당할 수 있도록 IPv6 지원을 필수로 정의하고 있다. 따라서 UMTS/GPRS 에서 IPv6 를 지원할 경우 이동망과 인터넷망간의 패킷 서비스 전달을 위해 게이트웨이 기능을 수행하는 GGSN 에서 가장 큰 변화가 이루어질 것이다. 그러므로 본 논문에서는 GGSN 이 dual stack 을 지원해야하는지에 대해 살펴본 후 UMTS/GPRS 프로토콜 구조를 제안한다. 그리고 IPv6 지원을 위해 GGSN의 기능을 설계하고 GTP 메시지와 IPv6 주소 할당 방법에 대해 살펴본다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1166-1174
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• 2004

In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2175-2178
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• 2005

Selective Laser Sintering(SLS) method is one of Rapid Prototyping(RP) technologies. It has been used to fabricate desirable part to sinter powder and stack the fabricated layer. Since the sintering process occurs using infrared laser having high thermal energy, shrinkage and curling of the fabricated part occurs according to thermal distribution. Therefore, the fast scanning path generation is necessary to eliminate the factors of quality deterioration. In case of fabricating larger size parts, the unique scanning device and scanning path generation should be considered. In this paper, the development of SLS machines being capable of large size fabrication(800${\times}$1000${\times}$800 mm, W${\times}$D${\times}$H) will be addressed. The dual laser system and the unique scanning device have been designed and built, which employ CO2 lasers and dynamic 3-axis scanners. The developed system allows scanning a larger planar surface with the desired laser spot size. Also, to generate the fast scanning paths, adaptive path generation is needed with respect to the shape of each layer, and not simply x, y scanning, but the scanning of arbitrary direction should be enabled. To evaluate the suggested method, the complex part will be used for the experiment fabrication.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.4
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• pp.215-221
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• 2007

IPv6 is a protocol to solve the address space limitation of IPv4 by IETF. Many transition mechanism to communicate between IPv4 and IPv6 in mixed IPv4/IPv6 network are proposed. DSTM tunneling is a mechanism that dual stack in IPv6 network is able to communicate with node in IPv4 network by dynamic allocating the IPv4 address. This mechanism supports the execution of IPv4 dependent application without modification at IPv6 network. In this paper, we explain the security vulnerability at DSTM network for DHCP attack, TEP attack, and source spoofing attack then describe the result of attacks.

• Journal of the Semiconductor & Display Technology
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• v.6 no.1 s.18
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• pp.17-22
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• 2007

Recent new packages such as MCP(Multi-Chip Package), QDP(Quadratic Die Package) and DDP(Dual Die Package) have stack type configuration. This kind of multi-layer package is thicker than single layer package. So there is need for the low height looping technology in wirebonder to make these packages thinner. There is stiff zone above ball in wirebonder wire which is called HAZ(Heat Affect Zone). When making low height loop (below $80\;{\mu}m$) with traditional forward loop, stiff wire in HAZ(Heat Affected Zone) above ball is bended and weakened. So the traditional forward looping method cannot be applied to low height loop. SSB(stand-off stitch) wire bonding method was applied to many packages which require very low loops. The drawback of SSB method is making frequent errors at making ball, neck damage above ball on lead and the weakness of ball bonding on lead. The alternative looping method is BNL(ball neckless) looping technology which is already applied to some package(DDP, QDP). The advantage of this method is faster in bonding process and making little errors in wire bonding compared with SSB method. This paper presents the result of BNL looping technology applied in assembly house and several issues related to low loop height consistence and BNL zone weakness.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.1
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• pp.75-83
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• 2008

In this paper, we propose an efficient algorithm that assigns single temporary IPv4 address and port number to improve efficiency of IPv4 address that is allocated in DSTM service. And, we have analyzed the elementary functions for DSTM and have designed the functional modules. Also, we have implemented the DTI interface for encapsulation and decapsulation of IPv6 packets. The performance analysis and comparison are investigated whether the appropriate interworking service is possible or not. Our observation results show that the performance of IPv4 over IPv6 tunneling is suitable to DSTM service due to the reduction of delay by eliminating checksum calculations in the header of IPv6 tunneling.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.628-630
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• 2005

IPv6는 기존 IPv4의 문제점인 주소 고갈 문제를 근본적으로 해결하기 위해 IETF(Internet Engineering Task Force)에서 제안한 프로토콜이다. 그러나 IPv4를 한 순간에 IPv6로 대체하는 것이 불가능하기 때문에 IPv4와 IPv6간의 호환 및 연동을 위해 듀얼스택(dual stack), 터널링(tunneling), 프로토콜 변환(protocol translation) 등 많은 IPv4-to-IPv6 transition 메커니즘들이 고려되고 있다. 이러한 프로토콜 진화 방안들은 각 방식에 따라 최소한 한 개 이상의 많은 공인 IPv4 주소를 필요로 하며 IPv4 주소가 부족한 현재 상황에서 IPv6 네트워크와의 연동에 않은 어려움이 따르게 된다. 본 논문에서는 공인 IPv4 주소 부족 문제와 네트워크 보안의 필요성에 의해, IPv4 사설 네트워크에서 공인 IPv4주소로 이루어진 네트워크(인터넷)와 IPv6 네트워크의 연동을 위해 단지 하나의 공인 IP 주소를 이용하여 네트워크간의 연동을 지원하는 통합 연동기를 설계한다.

• Journal of the Korean Society of Industry Convergence
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• v.20 no.2
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• pp.115-124
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• 2017

This paper aims to develop an SMPS topology for handling a high range of input voltages based on a DC-DC flyback converter circuit. For this purpose, 2 capacitors of the same specifications were serially connected on the input terminal side, with a flyback converter of the same circuit configuration serially connected to each of them, so as to achieve high input voltage and an effect of dividing input voltage. The serially connected flyback converters have the transformer turn ratio of 1:1, so that each coil is used for the winding of a single transformer, which is a characteristic of doubly-fed configuration and enables the correction of input capacitor voltage imbalance. In addition, a pulse transformer was designed and fabricated in a way that can achieve the isolation and noise robustness of the PWM output signal of the PWM controller that applies gate voltage to individual flyback converter switches. PSIM simulation was carried out to verify such a structure and confirm its feasibility, and a 100W class stack was fabricated and used to verify the feasibility of the proposed high voltage SMPS topology.