• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.1
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• pp.110-114
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• 2008

In this paper, high efficient class F power amplifier with dual band has been realized. Dual band power amplifier have used modify stub matching for single FET, center frequency 2.14GHz and 5.2GHz respectively. Dual band amplifier is 32.65dBm output power, gain 11dB and PAE 36% at the 2.14GHz, 7dB gain at the 5.2GHz. Design of a dual band class F power amplifier using harmonic control circuit. The measured are 9.9dB gain, 30dBm output power and PAE 55% at the 2.14GHz, 11.7dB gain at the 5.2GHz. This paper is being used the load-pull method and it maximizes output power and it is using the only one transistor in the paper. As a result, this research will obtain a dual band high PAE power amplifier.

• Journal of electromagnetic engineering and science
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• v.17 no.1
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• pp.20-28
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• 2017

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.9
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• pp.1437-1443
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• 2017

Electric energy is consumed or regenerated according to an operation of electric rail cars in urban railway power substations. A thyristor dual converter system is used to deal with the electric energy. Since the AC input voltage of power substations is $22.9kV{\pm}10%$, the magnitude of the AC voltage fluctuates according to load conditions, so the secondary side voltage of the DDY transformer also fluctuates. In the thyristor dual converter, the response characteristics of the DC output voltage and the DC output current are changed based on an initial firing angle in the cross mode conversion between the forward mode and the reverse mode. Therefore, this paper proposes the initial firing angle tracking algorithm considering fluctuation of the AC input voltage. The effectiveness of the proposed algorithm is verified by a simulation compared with the conventional algorithm.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2001.11a
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• pp.46-51
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• 2001

To reach high areal density, less track pitch is expected and more servo bandwidth is required. One approach to overcoming the problem is by using dual stage servo system. In this system, a voice coil motor (VCM) is used as the primary stage while a milliactuator is used as the secondary stage. We have suggested new milliactuator based on the shear mode of piezoelectric elements to drive the head suspension assembly. In this paper, we introduce controller design method, PQ method. PQ method reduces the controller design problem for DISO(dual-input/single-output) systems to two standard controller design problems for SISO(single-input/single-output) problems. The first part of PQ method directly address the issue of actuator output contribution, and the second part allows the use of traditional loop shaping to achieve the overall system performance. This paper shows how to employ the PQ method to meet aggressive close-loop performance specifications for a disk drive system with a VCM and piezoelectric milliactuator.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.142-145
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• 1999

In this paper, delay performances are evaluated and compared for three dual-plane switch architectures; dual input queue/dual switching plane (DQDP The terms of DQDP, DQDP-PS and DQDP-GQ were not used in [Turner88], [Lee96] and [Son97]. All these tern are designated in this letter for convenience.) switch, DQDP with plane selector (DQDP-PS) switch and DQDP based on output group queueing (DQDP-OGQ) switch. We show that under random traffic these switches give almost identical delay performances to that of the output queueing switch but under bursty traffic only the DQDP-PS and the DQDP-OGQ switches ran do.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.523-525
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• 2008

Novel zero-voltage switching(ZVS) dual inductor-fed DC-DC converter integrating a conventional dual inductor-fed boost converter(DIFBC) and a parallel bidirectional boost converter has been proposed. Most of current-fed type boost topologies including dual inductor schemes have crucial defects such as a high voltage spike on the main switch when it comes to turning off, an unattainable soft start-up due to the limited range of duty ratio, above 50%, and considerable switching losses due to the hard switching. By adding two auxiliary switches and an output capacitor on the conventional DIFBC, the proposed circuit can solve mentioned problems and improve the efficiency with simple methods. The operational principle and theoretical analysis of the proposed converter have been included. Experimental results based on a 42V input, 400V/1A output and 50kHz prototype are shown to verify the proposed scheme.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.155-158
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• 1999

This paper describe the design and measurements of dual PLL for IMT-2000 cellular phone. As a result, dual PLL was well-operated in the RF frequency ranges of 2300 ~ 2360 MHz and If frequency of 380 MHz. The output power of -4.28 ㏈m, phase noise of -107.66㏈c/Hz at 100KHz frequency offset, lock time of 675.6$mutextrm{s}$ were obtained at 2330MHz. The output power of -4.78 ㏈m, phase noise of -115.28㏈c/Hz were also obtained at 380MHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.23-28
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• 2007

A dual-band GaAs FET low noise amplifier (LNA) with an input LC-tank circuit is designed using inductance source feedback for wireless LAN, and output matching is realized with low-pass Cheyshev filter impedance transforming circuit. Some design techniques for dual band LNA have been developed including input and output design equations. The measured results shows close agreement with the predicted performance.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.134-141
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• 2022

This study presents a method for reducing current distortion that occurs when a dual-buck inverter generates reactive power. Dual-buck inverters, which are only capable of unity power factor operation, can generate reactive power capabilities by modifying a modulation technique. However, under non-unity power factor conditions, current distortion occurs at zero-crossing points of grid voltage and output current. This distortion is caused by parasitic capacitors, dead-time, and discontinuous conduction mode operation. This study proposes a modified modulation method to alleviate the current distortion at zero-crossing point of the grid voltage. A repetitive controller is applied to reduce this distortion of the output current. A 1 kVA prototype is built and tested. Simulation and experimental results demonstrate the effectiveness of the proposed method.

• Journal of IKEEE
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• v.17 no.3
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• pp.267-274
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• 2013

This paper presents a design of LLC resonant converter IC for LED backlight unit based on PFM/PWM dual-mode feedback. Dual output LLC resonant architecture with a single inductor is proposed, where the master output is controlled by the PFM and slave output is controlled by the PWM. To regulate the master output PFM is used as feedback to control the frequency of the power switch. On the other hand, PWM feedback is used to control the pulse width of the power switch and to regulate the slave output. This chip is fabricated in 0.35um 2P3M BC(Bipolar-CMOS-DMOS) Process and the die area is $2.3mm{\times}2.2mm$. Current consumptions is 26mA from 5V supply.