• Journal of Internet Computing and Services
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• v.10 no.5
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• pp.33-39
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• 2009

In this paper, the Window based dual-mode audio receiver of DAB and DAB+(Digital Audio Broadcasting Plus) is designed, and audio performance of it is analyzed. DAB+ can be composed of DAB and AAC(Advanced Audio Coding) for more effective audio services in the limited channel bandwidth. In the result of thesis, the Window based receiver can simultaneously be decoded for DAB/DAB+ dual-mode audio.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.280-287
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• 2006

Advent of the new European satellite positioning system, Galileo will result in development of new satellite receivers such as, GPS/Galileo dual mode receiver. Furthermore, a new GNSS satellite receiver would be required to be self-reconfigured to certain navigational environments like, indoor, high interference, integrity, etc. In this paper, design and implementation issue of a FPGA based flexible GNSS receiver which gets navigation solution using L1 band signals of GPS and Galileo simultaneously is addressed.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.1
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• pp.7-12
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• 2008

A GNSS(Global Navigation Satellite System) using GPS provides us with very useful information concerning the positioning of users in many sectors such as transportation, social services, the justice system and customs services, public works, search and rescue systems and leisure. A GNSS using the Galileo satellite is due to work in 2008 and expected to be used in various fields such as aviation, marine transportation, land surveying, resources development precise agriculture, telemetics, and so on. In this paper, we discuss the implementation and testing of a combined GPS/Galileo receiver which we named KSTAR V1.0. Each tracking module of GPS/Galileo dual mode correlator has the five track arms which consist of Very Early code, Early code, Prompt code, late code, and Very late code. Each of 24 tracking modules can be assigned to GPS and/or Galileo signal by changing mode selection register. The basic correlator integration dump period is set to 1ms for GPS C/A code and fast Galileo signal tracking. The performance of the developed combined GPS/Galileo receiver was tested and evaluated using the IF (Intermediated Frequency)-level GPS/Galileo signal generator.

• ETRI Journal
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• v.26 no.6
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• pp.555-559
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• 2004

We propose an efficient digital IF down converter architecture for dual-mode WCDMA/cdma2000 based on the concept of software defined radio. Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA and cdma2000. A sub-sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi-rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1047-1054
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• 2013

In this paper, we propose a dual-mode mixer to have multi-band radar signal receiver to be compact. The proposed mixer using a anti-parallel diode is operated as a fundamental mixer or sub-harmonic mixer with respect to a control voltage. A fundamental mixer with a control voltage show a conversion loss of -10 dB, 1dB compression point of 2 dBm at X-band. On the other hand, it is performed as a sub-harmonic mixer with a conversion loss of -10 dB, 1 dB compression point of 2 dBm at K-band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.51-57
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• 2010

A dual-mode direct conversion receiver is developed in $0.13\;{\mu}m$ RF CMOS process for IEEE 802.11n based wireless LAN and IEEE 802.16e based mobile WiMAX application. The RF receiver covers the frequency band between 2.3 and 2.7 GHz. Three-step gain control is realized in LNA by using current steering technique. Current bleeding technique is applied to the down-conversion mixer in order to lower the flicker noise. A frequency divide-by-2 circuit is included in the receiver for LO I/Q differential signal generation. The receiver consumes 56 mA at 1.4 V supply voltage including all LO buffers. Measured results show a power gain of 32 dB, a noise figure of 4.8 dB, a output $P_{1dB}$ of +6 dBm over the entire band.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.113-122
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• 2010

In this paper, we propose a CP (Cyclic Prefix) detection based SSS (Secondary Synchronization Signal) detection method for initial cell search in 3GPP LTE (3rd Generation Partnership Project Long Term Evolution) FDD/TDD (Frequency Division Duplex/Time Division Duplex) dual mode downlink receiver. In general, a blind coherent SSS detection method which can detect SSS without CP detection is applied. However, coherent detection method caused performance degradation by channel compensation error at high speed environment because it uses estimated CFR (Channel Frequency Response) at PSS (Primary Synchronization Signal), and it can be more serious problem in TDD mode due to increased distance between PSS and SSS. Also blind detectionhas the drawback of high computational complexity. Therefore, we proposed a CP type pre-decision structure with non-coherent SSS detection which has stable operation in high speed channel environments for 3GPP LTE TDD mode as well as FDD mode, and can reduce computational complexity by applying CP detection before SSS detection. Simulation results show that the proposed method has stable operation for 3GPP LTE TDD/FDD dual mode downlink receiver in various channel environments.

• The KIPS Transactions:PartD
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• v.15D no.1
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• pp.131-138
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• 2008

This paper describes the implementations of the first application service based on embedded Linux; Mobile Teller which uses WiBro network for data communications and CDMA network for voice communications. Currently, with the appearance of WiBro service, dual-mode terminals which support two heterogeneous networks are available. But, the development of applications which effectively use these networks for providing better service to user is rarely prepared. At Mobile Teller, when a sender on a dual-mode terminal types texts, the texts are transmitted to a TTS server located in the Internet through WiBro network. Subsequently, the TTS server converts the texts into voices and transmits the voice data to the dual-mode terminal. At last the dual-mode terminal sends the voice to the receiver through the CDMA network. In case of noisy environment or when a user has difficulty in speaking, Mobile Teller makes voice communication possible