• 제목/요약/키워드: Dual process

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이중마이크로프로세서의 이용과 분산처리기법을 도입한 선박용 원격제어 시스템의 설계에 관한 연구 (A Study on the Design of Ship's Distributed Remote Control System Using Dual-Microprocessor)

  • 홍순철;정경열;류길수
    • Journal of Advanced Marine Engineering and Technology
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    • 제18권5호
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    • pp.78-87
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    • 1994
  • In this paper design and implementation of ship's distributed remote control system using dual-microprocessor is presented for real time process. The proposed system is implemented with the single chip microprocessors in tightly coupled mode and results in speed up of $s_p$=1.74. Under the assumption that the nodes are interconnected in multidrop, the overall system performance such as average throughout-delay characteristics and effective throughput are analyzed using M/G/1 queneing model, and results show that the proposed node can be used in medium sized distributed monitoring and control system.

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스터트 및 아크 용접 겸용 로보트 시스템의 개발 (ON THE DEVELOPMENT OF STUD AND ARC WELDING DUAL-PURPOSE ROBOT SYSTEM)

  • 이용중;유범상
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1993년도 추계학술대회 논문집
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    • pp.582-587
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    • 1993
  • A robot application system is developed for dual purpose of stud welding and are welding to weld plates in the manufacturing of elevator cabin. The production quantity is not so big to accommodate separate stations for stud welding and are welding respectively while the need for randomization of the processes is urgent. A robot with specification for spot welding is chosen, which is appropriate for stud welding. Some implementations are made so that the robot may also be shared for are welding process. Common jig and fixture is designed for the dual purpose. Important aspects in the procedure of system design, installation, and commissioning are stated, and signal set-ups and logic diagrams are illustrated.

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Compact $H_2$ PSA 공정을 위한 흡착탑의 설계 (Design of adsorption bed for Compact H2 PSA process)

  • 이장재;이상진;문종호;최대기;이창하
    • 신재생에너지
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    • 제2권2호
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    • pp.60-68
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    • 2006
  • 소수 station의 수소분리정제를 위한 compact형 PSA 공정을 연구하였다. 기존 PSA 공정의 흡착탑이 차지하는 시스템의 공간을 줄이기 위하여 하나의 흡착탑 안에 다른 흡착탑을 넣어 흡착탑이 차지하는 공간을 최소화하였으며, 흡착탑 간의 열교환이 효과적으로 일어나도록 설계하였다. 수소 혼합물에 대한 활성탄으로 충진된 dual bed에서의 수소 혼합물에 대한 흡/탈착 동특성 실험을 실시하였으며, 시간에 따른 농도와 온도의 변화를 측정하였다. 수소 혼합물로는 $H_2/CO/CH_4/CO_2$ (69:2:3:26 vol.%) 를 사용하였으며, 흡착유량은 7LPM, 흡착압력은 9atm 조건에서 운전하였다. Inner bed와 outer bed의 성능은 각각의 열전달 특성의 차이로 인하여 다르게 나타났으나, 단일탑의 동특성보다는 우수한 성능을 보이고 있었다. 따라서 개발된 dual bed는 적은 부지를 차지하면서도, 보다 우수한 수소 분리 성능을 보일 수 있는 PSA 공정에 응용될 수 있음을 확인하였다.

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DMT(Dual Mode Trailer) 시스템 개발을 위한 기술성 분석

  • 이진우;이영진;조현철;한동섭;이성욱;한근조;이권순
    • 한국항해항만학회:학술대회논문집
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    • 한국항해항만학회 2007년도 추계학술대회 및 제23회 정기총회
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    • pp.233-235
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    • 2007
  • 현재 기존 철송 시스템에 있어서 문제점인 출발지와 목적지 사이 발생하는 복잡한 작업 프로세스(job process)를 간소화하여 철송 운임비감소와 물류운송의 체계 개선 및 활성화에 기여할 수 있는 시스템으로 DMT(Dual Mode Trailer) 시스템을 들 수 있다. 이에 본 기술의 국내적용 및 개발을 위해 기술동향 조사 및 국내 적용시 고려사항, 국내 적용 접합 모델 도출 등 그 기술성을 분석하였다.

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쌍대반응표면최적화의 방법론 및 응용 : A Literature Review (Methods and Applications of Dual Response Surface Optimization : A Literature Review)

  • 이동희;정인준;김광재
    • 대한산업공학회지
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    • 제39권5호
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    • pp.342-350
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    • 2013
  • Dual response surface optimization (DRSO), inspired by Taguchi's philosophy, attempts to optimize the process mean and variability by using response surface methodology. Researches on DRSO were extensively done in 1990's and have been matured recently. This paper reviews the existing DRSO methods from the decision making perspective. More specifically, this paper classifies the existing DRSO methods based on the optimization criterion and the timing of preference articulation. Also, some of case studies are reviewed. Extension to multiresponse optimization, triple response surface optimization, and application of data mining method are suggested as future research issues.

Image Restoration in Dual Energy Digital Radiography using Wiener Filtering Method

  • Min, Byoung-Goo;Park, Kwang-Suk
    • 대한의용생체공학회:의공학회지
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    • 제8권2호
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    • pp.171-176
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    • 1987
  • Wiener filtering method was applied to the dual energy imaging procedure in digital radiography(D.R.). A linear scanning photodiode arrays with 1024 elements(0.6mm H 1.3mm pixel size) were used to obtain chest images in 0.7 sec. For high energy image acquisition, X-ray tube was set at 140KVp, 100mA with a rare-earth phosphor screen. Low energy image was obtained with X-ray tube setting at 70KVp, 150mA. These measured dual energy images are represented in the vector matrix notation as a linear discrete model including the additive random noise. Then, the object images are restored in the minimum mean square error sense using Wiener filtering method in the transformed domain. These restored high and low energy images are used for computation of the basis image decomposition. Then the basis images are linearly combined to produce bone or tissue selective images. Using this process, we could improve the signal to noise ratio characteristics in the material selective images.

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펄스 레이저 증착법에 의한 YBCO 박막증착과 이중모드 공진기의 제작 (Fabrication of Novel Dual Mode Resonator Using Superconducting Thin Film Grown by Pulsed Laser Deposition)

  • 박주형;이상렬;안달
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 D
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    • pp.1546-1548
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    • 1998
  • Dual mode ring resonators(DMRR) have been fabricated using laser ablated $YBa_2Cu_3O_{7-x}$ superconducting thin films. The transition temperature of YBCO thin films were 85 - 88 K and the film thicknesses were about 5,000 $\AA$. Dual mode ring resonators were patterned by standard photolithography process and wet-etching. Then two-layer metal thin films (Ti/Ag) have been deposited for the ground plane on the back side of substrate by e-beam and thermal evaporation. The input/output feedline angles of each resonator were $60^{\circ}$, $100^{\circ}$, $180^{\circ}$. A network analyzer was used for testing the performance of the resonators in the frequency range of 6-13 GHz at 77 K.

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GSM / WCDMA 통신용 이중대역 CMOS 주파수 합성기 설계 (Design of a Dual band CMOS Frequency Synthesizer for GSM and WCDMA)

  • 한윤택;윤광섭
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2008년도 하계종합학술대회
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    • pp.435-436
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    • 2008
  • This paper presents a dual band frequency synthesizer for GSM and Wideband CDMA which is designed in a standard 0.13um CMOS 1P6M process. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider(128/129 DMP, 4bit PC, 3bit SC) and Low noise Ring-VCO. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 2mW power consumption by simulation. The simulated phase noise of VCO is -101dBc/Hz at 200kHz offset frequency from 1.9GHz.

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Dual CPU 기반 임베디드 웹 카메라 스트리밍 서버의 설계 및 구현 (Design and Implementation of A Dual CPU Based Embedded Web Camera Streaming Server)

  • 홍진기;문종려;백승걸;정선태
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 신호처리소사이어티 추계학술대회 논문집
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    • pp.417-420
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    • 2003
  • Most Embedded Web Camera Server products currently deployed on the market adopt JPEG for compression of video data continuously acquired from the cameras. However, JPEG does not efficiently compress the continuous video stream, and is not appropriate for the Internet where the transmission bandwidth is not guaranteed. In our previous work, we presented the result of designing and implementing an embedded web camera streaming server using MPEG4 codec. But the server in our previous work did not show good performance since one CPU had to both compress and process the network transmission. In this paper, we present our efforts to improve our previous result by using dual CPUs, where DSP is employed for data compression and StrongARM is used for network processing. Better performance has been observed, but it is found that still more time is needed to optimize the performance.

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A 2.7Gbps & 1.62Gbps Dual-Mode Clock and Data Recovery for DisplayPort in $0.18{\mu}m$ CMOS

  • Lee, Seung-Won;Kim, Tae-Ho;Lee, Suk-Won;Kang, Jin-Ku
    • 전기전자학회논문지
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    • 제14권1호
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    • pp.40-46
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    • 2010
  • This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using $0.18{\mu}m$ CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.