• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.742-750
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• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.1
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• pp.71-78
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• 2017

The electrical power system of Korean Utility Helicopter(KUH) is designed as a dual control system to enhance the system safety of aircraft and each system is installed separately at left and right of the aircraft. The system is composed of 2 AC generators, 1 APU generator, 2 Transformer Rectifier Units(TRU), AC/DC Electrical Master Box(AC/DC EMB). The AC/DC EMB, consists of 2 AC EMB and 2 DC EMB, is essential equipment which supply and distribute electric power to the aviation electronics and electrical equipment of KUH. There were defects caused by internal short circuit in AC EMB during the first production phase of the KUH. This paper describes the analysis of the defects, troubleshooting process, root cause, and the solution by design change.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.29-36
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• 2005

This paper presents the first hardware design of ARIA that KSA(Korea Standards Association) decided as the block encryption standard at Dec. 2004. The ARIA cryptographic algorithm has an efficient involution SPN (Substitution Permutation Network) and is immune to known attacks. The proposed ARIA design based on 1 cycle/round include a dual port ROM to reduce a size of circuit md a high speed round key generator with barrel rotator. ARIA design proposed is implemented with Xilinx VirtexE-1600 FPGA. Throughput is 437 Mbps using 1,491 slices and 16 RAM blocks. To demonstrate the ARIA system operation, we developed a security system cyphering video data of communication though Internet. ARIA addresses applications with high-throughput like data storage and internet security protocol (IPSec and TLS) as well as IC cards.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.2
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• pp.33-38
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• 2010

Recently, photovoltaic generator system is widely extended by energy policy of the government. Add to this, high efficiency of photocell power generation is steady needed to sun tracking method. However sun tracking method is not widely extended by insufficiency of tracking technology. As method of solving this problem, this paper applied sunlight sensor and neural network control algorithm for maximum power tracking of sun photocell. Sun tracking sensor consists of one upright square pole and form light sensor of east, west, south, north on flat board. Sun tracking dual axes control is operated respectively by two motor. Motor control input is calculated by neural network control algorithm. The function of proposed control method is verified by sun tracking experiment of photocell generation. The sun tracking method of this paper is increased 32[%] efficiency more than fixed method.

• International Journal of Naval Architecture and Ocean Engineering
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• v.11 no.2
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• pp.699-722
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• 2019

It is difficult to observe the potential risks of lifting or turn-over operations in the early stages before a real operation. Therefore, many dynamic simulations have been designed to predict the risks and to reduce the possibility of accidents. These simulations, however, have usually been performed for predetermined and fixed scenarios, so they do not reflect the real-time control of an operator that is one of the most important influential factors in an operation; additionally, lifting or turn-over operations should be a collaboration involving more than two operators. Therefore, this study presents an integrated method for a collaborative simulation that allows multiple workers to operate together in the virtual world. The proposed method is composed of four components. The first component is a dynamic analysis that is based on multibody-system dynamics. The second component is VR (virtual reality) for the generation of realistic views for the operators. The third component comprises the control devices and the scenario generator to handle the crane in the virtual environment. Lastly, the fourth component is the HLA (high-level architecture)-based integrated simulation interface for the convenient and efficient exchange of the data through the middleware. To show the applicability of the proposed method, it has been applied to a block turn-over simulation for which one floating crane and two crawler cranes were used, and an offshore module installation for which a DCR (dual-crane rig) was used. In conclusion, the execution of the proposed method of this study is successful regarding the above two applications for which multiple workers were involved.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.150-157
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• 2005

This paper presents the simulation modeling and analysis of variable wind speed turbine system(VWTS) using the doubly fed induction generator(DFIG) connected the back to back converter system in the rotor side. In the simulation, using the model system which has the 660[kW] rated power, blade control and the dual converter system are modeled for verifying the control characteristics. The VWTS is controlled by the optimal pitch angle for maximum output power under the rated wind speed, and for the rated output power over the rated wind speed. And also power factor is controlled by the reactive power. To verify the effectiveness of the proposed method, simulation results are compared with the actual data from the V47 VWTS located in Hangwon wind farm in Jeju-Do. According to the comparison of these results, this method shows excellent performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.7-13
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• 2009

This paper presents a multi-channel transceiver that achieves a data rate of 3.125Gb/s/ch. The LVDS is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. On the receiver side, a low-power CDR(clock and data recovery) using 1/4-rate clock based on dual-interpolator is proposed. The CDR generates needed additional clocks in each recovery part internally using only inverters. Therefore each part can be supplied with the same number of 1/4-rate clocks from a clock generator as in 1/2-rate clock method. Thus, the reduction of a clock frequency relaxes the speed limitation and lowers power dissipation. The prototype chip is comprised of two channels and was fabricated in a $0.18{\mu}m$ standard CMOS process. The output jitter of transmitter is loops, peak-to-peak(0.31UI) and the measured recovered clock jitter is 47.33ps, peak-to-peak which is equivalent to 3.7% of a clock period. The area of the chip is $3.5mm^2$ and the power consumption is about 119mW/ch.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.