• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.802-809
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• 2014

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.2
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• pp.72-75
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• 2012

In this paper, high-efficiency DC-AC converter is implemented for the wireless power transmission. The DC-AC converter is implemented by combining the oscillator and power amplifier. Because the conversion efficiency of wireless power transmitter is strongly affected by the efficiency of power amplifier, the high-efficiency power amplifier is implemented by using the Class-E amplifier structure. Also, because the output power of oscillator connected to the input stage of power amplifier is low, high-gain two-stages power amplifier using the drive amplifier is implemented to realize the high-output power DC-AC converter. The dual band harmonic suppression filter is implemented to suppress 2nd, 3rd harmonics of 13.56 MHz. The output power and conversion efficiency of DC-AC converter are 40 dBm and 80.2 % at the operation frequency of 13.56 MHz.

• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.119-124
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• 2014

In this paper, A GSm/WCDMA band antenna which can be confirmed positioning information of a container by using the GPS/GLONASS bands on one board and can be sent the positioning information to the mobile communication network in real time is designed. A microstrip patch antennas which supports dual-band (GPS and GLONASS) was optimized. The antenna size is $25{\times}25{\times}5[mm]$. A chip monopole antennas which supports dual-band (GSM and WCDMA) was optimized. The antenna size is $27{\times}8{\times}3.2[mm]$. To amplify the Satellite reception signal level, two-stage low noise amplifier(LNA) was designed. The LNA gain is 27[dB]. The size of Jig for antennas measuring is $100{\times}30{\times}1[mm]$.

• Journal of IKEEE
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• v.23 no.3
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• pp.917-924
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• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.2
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• pp.175-180
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• 2015

In this paper, GPS / GLONASS receiving a small active antenna is proposed. A microstrip patch antenna which supports dual-band (GPS and GLONASS) was optimized. The antenna size is $13{\times}13{\times}3.6mm$. The jig was changed to confirm the proposed antenna characteristic size, was adjusted to feed gap of the patch antenna, it was confirmed by change in LNA shield case or not. The antenna jig size is $65.6{\times}13{\times}0.8mm$. The maximum gain of the GPS band is 3.78dBi, the maximum gain of the GLONASS bands is 4dBi. To amplify the Satellite reception signal level, one-stage low noise amplifier(LNA) was designed. The LNA chip was using the BGA715 N7, the LNA gain is 19.9dB. The utilization possibility of the GPS / GLONASS receiving a small active antenna could be confirmed according to compare and analyze the simulation and measurement data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.141-142
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• 2006

본 논문에서는 단일 FET를 이용하여 900MHz/2.14GHz 이중 대역 고효율 도허티 전력증폭기 설계 구현을 하였다. 이중대역 도허티 전격증폭기의 출력전력은 900MHz 에서 35.91dBm, 2.14GHz에서 35.91 dBm의 출력을 얻었으며, 전력부가효율은 900MHz에서 40.32%, 2.14GHz에서는 40.47%의 효율을 획득 하였다. 또한 본 논문에서 단 하나의 능등소자를 이용하여 최대한의 출력전력을 얻기 위하여 최대 전력정합법을 사용하였으며 그 결과 이중대역 전력증폭기를 구현할 수 있었다.

• The Journal of the Acoustical Society of Korea
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• v.31 no.7
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• pp.480-486
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• 2012

In the design of electro acoustic transducer, power factor improvement circuit is more required rather than impedance matching if the driving power amplifier has little inner resistance. Many research results have been focused on the power matching circuit designing for transferring maximum power in the wideband. There are few results in the designing study on the power factor improvement for the wide band electro acoustic transducer. In this paper, we propose a new design method on the power factor improvement for the wide band electro acoustic transducer. The proposed method consists of two steps, the chebyschev matching method and the constrained optimization, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.12
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• pp.967-975
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• 2013

In the design of underwater electro acoustic transducer, power factor improvement circuit is more required rather than impedance matching if the driving power amplifier has little inner resistance. Many research results have been focused on the power matching circuit designing for transferring maximum power in the wideband. There are few results in the designing study on the power factor improvement for the wide band underwater electro acoustic transducer. In this paper, we set up a new design method on the power factor improvement for the wide band electro acoustic transducer, and confirm its feasibility by the experiments.