• Title/Summary/Keyword: Dual Input

Search Result 492, Processing Time 0.03 seconds

Design of Single Power CMOS Beta Ray Sensor Reducing Capacitive Coupling Noise (커패시터 커플링 노이즈를 줄인 단일 전원 CMOS 베타선 센서 회로 설계)

  • Jin, HongZhou;Cha, JinSol;Hwang, ChangYoon;Lee, DongHyeon;Salman, R.M.;Park, Kyunghwan;Kim, Jongbum;Ha, PanBong;Kim, YoungHee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
    • /
    • v.14 no.4
    • /
    • pp.338-347
    • /
    • 2021
  • In this paper, the beta-ray sensor circuit used in the true random number generator was designed using DB HiTek's 0.18㎛ CMOS process. The CSA circuit proposed a circuit having a function of selecting a PMOS feedback resistor and an NMOS feedback resistor, and a function of selecting a feedback capacitor of 50fF and 100fF. And for the pulse shaper circuit, a CR-RC2 pulse shaper circuit using a non-inverting amplifier was used. Since the OPAMP circuit used in this paper uses single power instead of dual power, we proposed a circuit in which the resistor of the CR circuit and one node of the capacitor of the RC circuit are connected to VCOM instead of GND. And since the output signal of the pulse shaper does not increase monotonically, even if the output signal of the comparator circuit generates multiple consecutive pulses, the monostable multivibrator circuit is used to prevent signal distortion. In addition, the CSA input terminal, VIN, and the beta-ray sensor output terminal are placed on the top and bottom of the silicon chip to reduce capacitive coupling noise between PCB traces.

Dual Dictionary Learning for Cell Segmentation in Bright-field Microscopy Images (명시야 현미경 영상에서의 세포 분할을 위한 이중 사전 학습 기법)

  • Lee, Gyuhyun;Quan, Tran Minh;Jeong, Won-Ki
    • Journal of the Korea Computer Graphics Society
    • /
    • v.22 no.3
    • /
    • pp.21-29
    • /
    • 2016
  • Cell segmentation is an important but time-consuming and laborious task in biological image analysis. An automated, robust, and fast method is required to overcome such burdensome processes. These needs are, however, challenging due to various cell shapes, intensity, and incomplete boundaries. A precise cell segmentation will allow to making a pathological diagnosis of tissue samples. A vast body of literature exists on cell segmentation in microscopy images [1]. The majority of existing work is based on input images and predefined feature models only - for example, using a deformable model to extract edge boundaries in the image. Only a handful of recent methods employ data-driven approaches, such as supervised learning. In this paper, we propose a novel data-driven cell segmentation algorithm for bright-field microscopy images. The proposed method minimizes an energy formula defined by two dictionaries - one is for input images and the other is for their manual segmentation results - and a common sparse code, which aims to find the pixel-level classification by deploying the learned dictionaries on new images. In contrast to deformable models, we do not need to know a prior knowledge of objects. We also employed convolutional sparse coding and Alternating Direction of Multiplier Method (ADMM) for fast dictionary learning and energy minimization. Unlike an existing method [1], our method trains both dictionaries concurrently, and is implemented using the GPU device for faster performance.

Implementation of A Millimeter-Wave Multiflare-Angle Horn Antenna (밀리미터파 다중개구각 혼안테나 구현)

  • Oh, Kyung-Hyun;Kim, Ji-Hyung;Yang, Seung-Sik;Shin, Sang-Jin;Cho, Young-Ho;Lee, Byung-Ryul;Ahn, Bierng-Chearl
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.29 no.1
    • /
    • pp.36-41
    • /
    • 2018
  • This paper presents an implementation of a millimeter-wave(W band) multiflare-angle horn antenna. The proposed antenna is a multimode dual-polarized square horn having equal E- and H-plane beamwidths and consists of a multimode generating section, a four-square-waveguide exciter, orthomode transducers, and power combiners for the sum pattern formation. The antenna structure has been designed to allow for easy fabrication and the designed antenna has been fabricated to a precision of ${\pm}0.02mm$ by layer-by-layer machining and diffusion bonding. The input reflection coefficient and the radiation pattern of the fabricated antenna have been measured using a network analyzer and a far-field test facility. Measurements show that the proposed antenna has 17.7~18.3 dBi gain, $25.2{\sim}28.5^{\circ}$ beamwidth, and an input VSWR between 1.02~1.75, within ${\pm}0.5GHz$ from the center frequency.

Damping Analysis using IEEEST PSS and PSS2A PSS

  • Lee Sang-Seung;Kang Sang-Hee;Jang Gwang-Soo;Li Shan-Ying;Park Jong-Keun;Moon Seung-Il;Yoon Yong-Tae
    • Journal of Electrical Engineering and Technology
    • /
    • v.1 no.3
    • /
    • pp.271-278
    • /
    • 2006
  • This paper scrutinized the damping effects of installing the prototype PSSs by a transient analysis for eight buses of faults in the South Korean power system. The PSSs used have the co-PSS blocks for IEEEST model with a single input and the co+power PSS blocks for PSS2A model with dual inputs. The simulation tool was a TSAT(Transient Security Assessment Tool) developed by Powertech Labs Inc. The voltages of the transmission line for simulations were 765kV and 345kV, and the faults for eight cases were sequenced by considering the open state and the close state of the lines. In the simulations, the three-phase line to ground (L-G) fault generated different points for each region. The simulations were compared to the cases of no PSS, partial IEEEST and PSS2A, absolute IEEEST, and absolute PSS2A to show that the power system oscillation can be effectively damped by PSS modules. Simulations were conducted to confirm the effectiveness for the KEPCO (Korea Electric Power Corporation) power system.

Multiple-inputs Dual-outputs Process Characterization and Optimization of HDP-CVD SiO2 Deposition

  • Hong, Sang-Jeen;Hwang, Jong-Ha;Chun, Sang-Hyun;Han, Seung-Soo
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.11 no.3
    • /
    • pp.135-145
    • /
    • 2011
  • Accurate process characterization and optimization are the first step for a successful advanced process control (APC), and they should be followed by continuous monitoring and control in order to run manufacturing processes most efficiently. In this paper, process characterization and recipe optimization methods with multiple outputs are presented in high density plasma-chemical vapor deposition (HDP-CVD) silicon dioxide deposition process. Five controllable process variables of Top $SiH_4$, Bottom $SiH_4$, $O_2$, Top RF Power, and Bottom RF Power, and two responses of interest, such as deposition rate and uniformity, are simultaneously considered employing both statistical response surface methodology (RSM) and neural networks (NNs) based genetic algorithm (GA). Statistically, two phases of experimental design was performed, and the established statistical models were optimized using performance index (PI). Artificial intelligently, NN process model with two outputs were established, and recipe synthesis was performed employing GA. Statistical RSM offers minimum numbers of experiment to build regression models and response surface models, but the analysis of the data need to satisfy underlying assumption and statistical data analysis capability. NN based-GA does not require any underlying assumption for data modeling; however, the selection of the input data for the model establishment is important for accurate model construction. Both statistical and artificial intelligent methods suggest competitive characterization and optimization results in HDP-CVD $SiO_2$ deposition process, and the NN based-GA method showed 26% uniformity improvement with 36% less $SiH_4$ gas usage yielding 20.8 ${\AA}/sec$ deposition rate.

Shake table responses of an RC low-rise building model strengthened with buckling restrained braces at ground story

  • Lee, Han Seon;Lee, Kyung Bo;Hwang, Kyung Ran;Cho, Chang Seok
    • Earthquakes and Structures
    • /
    • v.5 no.6
    • /
    • pp.703-731
    • /
    • 2013
  • In order to verify the applicability of buckling restrained braces (BRB's) and fiber reinforced polymer (FRP) sheets to the seismic strengthening of a low-rise RC building having the irregularities of a soft/weak story and torsion at the ground story, a series of earthquake simulation tests were conducted on a 1:5 scale RC building model before, and after, the strengthening, and these test results are compared and analyzed, to check the effectiveness of the strengthening. Based on the investigations, the following conclusions are made: (1) The BRB's revealed significant slips at the joint with the existing RC beam, up-lifts of columns from RC foundations and displacements due to the flexibility of foundations, and final failure due to the buckling and fracture of base joint angles. The lateral stiffness appeared to be, thereby, as low as one seventh of the intended value, which led to a large yield displacement and, therefore, the BRB's could not dissipate seismic input energy as desired within the range of anticipated displacements. (2) Although the strengthened model did not behave as desired, great enhancement in earthquake resistance was achieved through an approximate 50% increase in the lateral resistance of the wall, due to the axial constraint by the peripheral BRB frames. Finally, (3) whereas in the original model, base torsion was resisted by both the inner core walls and the peripheral frames, the strengthened model resisted most of the base torsion with the peripheral frames, after yielding of the inner core walls, and represented dual values of torsion stiffness, depending on the yielding of core walls.

Experimental investigation of Scalability of DDR DRAM packages

  • Crisp, R.
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.17 no.4
    • /
    • pp.73-76
    • /
    • 2010
  • A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

2.6 GHz-Band MIMO Omni Antenna Having Folded Configuration (폴디드 구조를 갖는 2.6 GHz 대역 MIMO 무지향 안테나)

  • Lee, Su-Won;Lee, Jae-Du;Lee, Hai-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.26 no.2
    • /
    • pp.127-134
    • /
    • 2015
  • In this paper, we propose 2.6 GHz single band dual polarization MIMO omni antenna for in-building applications. The proposed antenna operates at 2.6 GHz single LTE band, Up-link 2.52~2.54 GHz and Down-link 2.64~2.66 GHz. Horizontal and vertical polarizations of the antenna has been, respectively, constructed by the synthesis of four folded loop antennas and the folded monopole antenna. The height of the MIMO omni-directional antenna is minimized to be less than ${\lambda}/13.5$ from the ground. The measurement results show excellent MIMO omni antenna performance of 2.85 dBi vertical polarization gain, 2.29 dBi horizontal polarization gain, and 19.25 dB port isolation.

An experimental study on the cooling performance and the phase shift between piston and displacer in the Stirling cryocooler

  • Park, S. J.;Y. J. Hong;Kim, H. B.;D. Y. Koh;B. K. Yu;Lee, K. B.
    • Progress in Superconductivity and Cryogenics
    • /
    • v.5 no.1
    • /
    • pp.111-117
    • /
    • 2003
  • In the design of the split type free displacer Stilting cryocooler the motion of the displacer is very important to decide the cooling capacity, which depends upon the working gas pressure, the swept volume in the compression space and the expansion space, operating frequency, the phase shift between piston and displacer, etc. In this study, Stirling cryocooler actuated by the electric farce of the dual linear motor is designed and manufactured. Cool down characteristics of the cold end with laser displacement sensor in the expander of the Stilting cryocooler is evaluated. The charging pressure was 15kg$_{f}$/$\textrm{cm}^2$ and operating frequency was 50Hz. Input power and the lowest temperature were about 32W and 67K, respectively. And, displacement of the piston is measured by LVDTs (Linear Variable Differential Transformers), displacement of thedisplacer is measured by laser optic method, and phase shift between piston and displacer is discussed. As the peak-to-peak pressure of the compressor was increased, peak-to-peak displacement of the displacer was increased. The peak-to-peak displacement of the displacer increases in the range of 0 - 64.5Hz(resonant frequency of the displacer), but decreases steeply when the operating frequency is bigger than the resonant frequency. Finally when the phase shift between displacements of the Piston and displacer is 45。, operating frequency is optimum and is decided by resonant frequency of the expander, mass and cross section area of the displacer and constant by friction and flow resistance.e.

Low Power 31.6 pJ/step Successive Approximation Direct Capacitance-to-Digital Converter (저전력 31.6 pJ/step 축차 근사형 용량-디지털 직접 변환 IC)

  • Ko, Youngwoon;Kim, Hyungsup;Moon, Youngjin;Lee, Byuncheol;Ko, Hyoungho
    • Journal of Sensor Science and Technology
    • /
    • v.27 no.2
    • /
    • pp.93-98
    • /
    • 2018
  • In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.