• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.143-149
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• 2016

The two-stage converter is widely used in traditional DC/AC inverter. It has several disadvantages such as complex topology, large volume and high loss. In order to overcome these shortcomings, a novel half load-cycle worked dual SEPIC single-stage inverter, which is based on the analysis of the relationship between input and output voltages of SEPIC converters operating in the discontinuous conduction mode (DCM), is presented in this paper. The traditional single-stage inverter has remarkable advantages in small and medium power applications, but it can’t realize boost DC/AC output directly. Besides one pre-boost DC/DC converter is needed between the DC source and the traditional single-stage inverter. A novel DC/AC inverter without pre-boost DC/DC converter, which is comprised of two SEPIC converters, is studied. The output of dual SEPIC converters is connected with anti-parallel and half load-cycle control is used to realize boost and buck DC/AC output directly and work properly, whatever the DC input voltage is higher or lower than the AC output voltage. The working principle, parameter selection and the control strategy of the inverters are analyzed in this paper. Simulation and experiment results verify the feasibility of the new inverter.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2057-2066
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• 2016

An extension of the one-cycle control (OCC) method for switched-capacitor (SC) converters is proposed in this paper, featuring a fast dynamic response, wide line and load operation ranges, and simplicity in implementation. To illustrate the operation principle of this nonlinear control method and to demonstrate its simplicity in design, a dual-phase unity gain SC converter is examined. A new control loop based on the charge balance in a flying capacitor is formulated for the OCC technique and implemented with a 15W dual-phase unity gain SC converter on a circuit board for control verification. The obtained experimental results show that external disturbances can be rejected in one switching cycle by the OCC controlled SC converter with good line and load regulations. When compared to other control methods, the proposed nonlinear control loop exhibits superior dynamic performance in suppressing input and load disturbances.

• Journal of the Society of Naval Architects of Korea
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• v.49 no.1
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• pp.33-44
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• 2012

In this study, the optimal operating conditions for the dual mixed refrigerant(DMR) cycle were determined by considering the power efficiency. The DMR cycle consists of compressors, heat exchangers, seawater coolers, valves, phase separators, tees, and common headers, and the operating conditions include the equipment's flow rate, pressure, temperature, and refrigerant composition per flow. First, a mathematical model of the DMR cycle was formulated in this study by referring to the results of a past study that formulated a mathematical model of the single mixed refrigerant(SMR) cycle, which consists of compressors, heat exchangers, seawater coolers, and valves, and by considering as well the tees, phase separators, and common headers. Finally, in this study, the optimal operating conditions from the formulated mathematical model was obtained using a hybrid optimization method that consists of the genetic algorithm(GA) and sequential quadratic programming(SQP). Moreover, the required power at the obtained conditions was decreased by 1.4% compared with the corresponding value from the past relevant study of Venkatarathnam.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.16-21
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• 2002

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.29-34
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• 2005

This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.

• 연구논문집
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• s.27
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• pp.75-86
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• 1997

Combined cycle power plant is a system where a gas turbine or steam turbine is used to produce shaft power to drive a generator for producing electrical power and the steam from the HRSG is expanded in a steam turbine for additional shaft power. Combined cycle plant is a one from of cogeneration. The temperature of the exhaust gases from a gas turbine ranges from $400^\circC$ to $600^\circC$, and can be used effectively in a heat recovery steam generator to produce steam. Combined cycle can be classed as a "topping(gas turbine)" and a "bottoming(steam turbine)" cycle. The first cycle, to which most of the heat is supplied, is called the topping cycle. The wasted heat it produces is then utilized in a second process which operates at a lower temperature level and is therefore referred to as a "bottoming cycle". The combination of gas/steam turbine power plant managed to be accepted widely because, first, each individual system has already proven themselves in power plants with a single cycle, therefore, the development costs are low. Secondly, the air as a working medium is relatively non-problematic and inexpensive and can be used in gas turbines at an elevated temperature level over $1000^\circC$. The steam process uses water, which is likewise inexpensive and widely available, but better suited for the medium and low temperature ranges. It, therefore, is quite reasonable to use the steam process for the bottoming cycle. Only recently gas turbines attained inlet temperature that make it possible to design a highly efficient combined cycle. In the present study, performance analysis of a dual pressure combined-cycle power plant is carried out to investigate the influence of topping cycle to combined cycle performance.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.779-782
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• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• Korean Journal of Social Welfare
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• v.45
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• pp.288-314
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• 2001

The purpose of this study is to examine the strategies that may influence the marital satisfaction of dual-earner men and women. General linear model, Pearson's correlation analysis, Stepwise multiple regression were employed for data analysis. the subjects are 396 dual-earner men and women. The result from the research were as follows: 1) coping strategy use differs significantly by life cycle stage. 2) The following strategies significantly correlated with the level of marital satisfaction: cognitive restructuring, delegation. using social support, modifying standards, personal time reducing. 3) The result of stepwise multiple regression analysis indicated that strategies which predict the level of marital satisfaction were cognitive restructuring, delegating, using social support, personal time reducing. these finding give us significant practical implications for social work intervention.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.79-86
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• 2004

This paper proposes a dual band Voltage Controlled Oscillator(VCO) with a standard 0.3${\mu}{\textrm}{m}$ CMOS process to generate 1.07GHz and 2.07GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder(HA) was capable of producing a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561MHz/V and 14.6mW, respectively. The phase noises of the dual band VCO are measured to be -102.55dBc/Hz and -95.88dBc/Hz at 2MHz offset from 1.07GHz and 2.07GHz, respectively.

• Journal of Power Electronics
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• v.15 no.1
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• pp.268-277
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• 2015

In this paper, a dual-converter three-phase pulse width modulation (PWM) rectifier based on unbalanced one-cycle control (OCC) strategy is proposed. The proposed rectifier is used to eliminate the second harmonic waves of DC voltage and distortion of line currents under unbalanced input grid voltage conditions. The dual-converter PWM rectifier employs two converters, which are called positive-sequence converter and negative-sequence converter. The unbalanced OCC system compensates feedback currents of positive-sequence converter via grid negative-sequence voltages, as well as compensates feedback currents of negative-sequence converter via grid positive-sequence voltages. The AC currents of positive- and negative-sequence converter are controlled to be symmetrical. Thus, the workload of every switching device of converter is balanced. Only one conventional PI controller is adopted to achieve invariant power control. Then, the parameter tuning is simplified, and the extraction for positive- and negative-sequence currents is not needed anymore. The effectiveness and the viability of the control strategy are demonstrated through detailed experimental verification.