• Title/Summary/Keyword: Drain material

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Fabrication and Characterization of MFIS-FET using Au/SBT/LZO/Si structure

  • Im, Jong-Hyun;Lee, Gwang-Geun;Kang, Hang-Sik;Jeon, Ho-Seung;Park, Byung-Eun;Kim, Chul-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.174-174
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    • 2008
  • Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

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Influence of Source/Drain Electrodes on the Properties of Zinc Tin Oxide Transparent Thin Film Transistors (Zinc Tin Oxide 투명 박막트랜지스터의 특성에 미치는 소스/드레인 전극의 영향)

  • Ma, Tae Young;Cho, Mu Hee
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.28 no.7
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    • pp.433-438
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    • 2015
  • Zinc tin oxide transparent thin film transistors (ZTO TTFTs) were fabricated by using $n^+$ Si wafers as gate electrodes. Indium (In), aluminum (Al), indium tin oxide (ITO), silver (Ag), and gold (Au) were employed for source and drain electrodes, and the mobility and the threshold voltage of ZTO TTFTs were observed as a function of electrode. The ZTO TTFTs adopting In as electrodes showed the highest mobility and the lowest threshold voltage. It was shown that Ag and Au are not suitable for the electrodes of ZTO TTFTs. As the results of this study, it is considered that the interface properties of electrode/ZTO are more influential in the properties of ZTO TTFTs than the conductivity of electrode.

2D-Simulation of Quantum Effects in Silicon Nanowire Transistor (실리콘 나노선 트렌지스터 양자 효과의 2차원 시뮬레이션)

  • Hwang, Min-Young;Choi, Chang-Yong;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.132-132
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    • 2009
  • A 2D-simulation using a quantum model of silicon nanowire (SiNW) field-effect transistors (FETs) have been performed by the effective mass theory. We have investigated very close for real device analysis, so we used to the non-equilibrium Green's function (NEGF) and the density gradient of quantum model. We investigated I-V characteristics curve and C-V characteristics curve of the channel thickness from 5nm to 200nm. As a result of simulation, even higher drain current in SiNW using a quantum model was observed than in SiNW using a non-quantum model. The reason of higher drain current can be explained by the quantum confinement effect.

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A Study on the Impedance Effect of Nonvolatile SNOSEFT EFFPROM Memory Devices (비휘발성 SNOSEFT EFFPROM 기억소자의 임피던스 효과에 관한 연구)

  • 강창수;김동진;김선주;이상배;이성배;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1995.05a
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    • pp.86-89
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    • 1995
  • In this pacer, The effect of the impedances in SNOSEFT s memory devices has been developed. The effect of source and drain impedances are measuring using the method of the field effect bias resistance in the inner resistance regions of the device structure and external bias resistance. The effect of impedance by source and drain resistance shows according to increasing to the storage of memory charges, shows according to a function of decreasing to the gate voltages, shows the delay of threshold voltages, The delay time of low conductance state and high conductance state by the impedance effect shows 3 [${\mu}$sec] and 1[${\mu}$sec] respectively.

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Memory Characteristics of 1T-DRAM Cell by Channel Structure (채널 구조에 따른 1T-DRAM Cell의 메모리 특성)

  • Jang, Ki-Hyun;Jung, Seung-Min;Park, Jin-Kwon;Cho, Won-Ju
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.2
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    • pp.96-99
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    • 2012
  • We fabricated fully depleted (FD) SOI-based 1T-DRAM cells with planar channel or recessed channel and the electrical characteristics were investigated. In particular, the dependence of memory operating mode on the channel structure of 1T-DRAM cells was evaluated. As a result, the gate induced drain leakage current (GIDL) mode showed a better memory property for planar type 1T-DRAM. On the other hand, the impact ionization (II) mode is more effective for recessed type.

Performance of capacitorless 1T-DRAM cell on silicon-germanium-on-insulator (SGOI) substrate (SGOI 기판을 이용한 1T-DRAM에 관한 연구)

  • Jung, Seung-Min;Oh, Jun-Seok;Kim, Min-Soo;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.346-346
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    • 2010
  • A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

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Fabrication and New Model of Saturated I-V Characteristics of Hydrogenerated Amorphous Silicon Thin Film Transistor (비정질 실리콘 박막 트랜지터 포화전압 대 전류특성의 새로운 모델)

  • Lee, Woo-Sun;Kang, Yong-Chul;Yang, Tae-Hwan;Chung, Hae-In
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1992.11a
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    • pp.3-6
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    • 1992
  • A new analytical expression for the saturated I-V characteristics of hydrogenerated amorphous silicon thin film transistors(a-si:H TFT) is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled. The model is based on three functions obtained from the experimental data of $I_D$ versus $V_G$. Theoretical results confirm the simple form of the model in terms of the device geometry. It was determined that the saturated drain current increased at a fixed gate voltage and the device saturated at increasingly larger drain voltages while the threshold voltages decreased.

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The GaAs Leakage Current Characteristics of GaAs MESFET's using Source Ground Status (GaAs MESFET의 Source 접지상태에 따른 게이트 누설 전류 특성)

  • Won, Chang-Sub;Yu, Young-Han;Ahn, Hyung-Keun;Han, Deuk-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.263-266
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    • 2003
  • The gate leakage current is first calculated using the experimental method between gate and drain by opening source electrode. Next, the gate to drain current has been obtained with a ground source. The difference of two current has been tested and provide that the existence of another source to Schotuy barrier height against the image force lowering effect.

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Potential Barrier Shift Caused by Channel Charge in Short Channel GaAs MESFET (Short Channel GaAs MESFET의 채널전하분포와 채널전하에 의한 전위장벽의 변화)

  • Sub, Won-Chang;Lee, Myung-Soo;Ryu, Se-Hwan;Han, Deuk-Young;Ahn, Hyung-Keun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.9
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    • pp.793-799
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    • 2006
  • In this paper, the gate leakage current is first calculated using the experimental method between gate and drain by opening source electrode. the gate to drain current has been obtained with ground source. The difference between two currents has been tested and proves that the electric field generated by channel charge effect against the image force lowering.

Study on Organic Thin-Film Transistors(OTFTs) Devices with Gold and Nickel/Silver electrodes (전극에 따른 유기박막트랜지스터 소자의 전기적 특성 연구)

  • Hwang, Seon-Wook;Hyung, Gun-Woo;Park, Il-Houng;Choi, Hak-Bum;Kim, Young-Kwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.271-272
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    • 2008
  • We fabricated a pentacene thin-film transistor with Ni/Ag source/drain electrodes. Also, we obtained similar electrical characteristics as compared with source/drain electrode with Au. This device was found to have a field-effect mobility of about 0.021 $cm^2$/Vs, a threshold voltage of -5, -7 V, an subthreshold slope of 2.0, 4.5 V/decade, and an on!off current ratio of $3.6\times10^5$, $2.0\times10^6$.

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