• Transactions on Electrical and Electronic Materials
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• 제12권3호
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• pp.93-97
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• 2011

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 ${\mu}M$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 ${\mu}M$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($I_{SUB}$), drain to source leakage current ($I_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2010년도 추계 학술발표회 2차
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• pp.3-12
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• 2010

Vertical drains have been commonly used to increase the rate of the consolidation of dredged material. The installation of vertical drains additionally provides a radial flow path in the dredged foundation. The objective of this study develops a numerical model for 2-D axisymmetric non-linear finite strain consolidation considering self-weight consolidation to predict the effect of vertical drain in dredged foundation which is in process of self-weight consolidation. The non-linear relationship between the void ratio and effective stress and permeability during consolidation are taken into account in the numerical model. The results of the numerical analysis are compared with that of the self-weight consolidation test in which an artificial vertical drain is installed. In addition, the numerical model developed in this paper is the simplified analytical method proposed by Ahn et, al (2010). The comparisons show that the developed numerical model can properly simulate the consolidation of the dredged material with the vertical drains installed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.171-172
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• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2003년도 봄 학술발표회 논문집
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• pp.349-356
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• 2003

Almost every material of PVD (Prefabricated Vertical Drain) has the fatal problem on the condition - the length must shorten with the settlement of the surrounding grounds - which all PVDs must satisfy. Kinking deformation by buckling of PVD due to consolidation settlement Is discussed in this paper. A new testing device to clarify the deformation of PVD under consolidation of surrounding clay was developed and the fiber drain and a PVD made of plastics were compared under the same condition of consolidation using natural clay specimens. The results are also shown in this paper.

• Transactions on Electrical and Electronic Materials
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• 제17권3호
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• pp.143-145
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• 2016

In order to find suitable source and drain (S/D) electrodes for amorphous InGaZnO thin film transistors (a-IGZO TFTs), the specific contact resistance of interface between the channel layers and various S/D electrodes, such as Ti/Au, a-IZO and multilayer of a-IGZO/Ag/a-IGZO, was investigated using the transmission line model. The a-IGZO TFTs with a-IGZO/Ag/a-IGZO of S/D electrodes had good performance and low contact resistance due to the homo-junction with channel layer. The stability was measured with different electrodes by a positive bias stress test. The result shows the a-IGZO TFTs with a-IGZO/Ag/a-IGZO electrodes were more stable than other devices.

• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• 한국전기전자재료학회논문지
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• 제33권5호
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• pp.427-431
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• 2020

In this research, we evaluated the electrical properties of polycrystalline-gallium-oxIde (Ga₂O₃) thin films grown by mist-CVD. A 500~800 nm-thick Ga₂O₃ film was used as a channel in a fabricated bottom-gate MOSFET device. The phase stability of the β-phase Ga₂O₃ layer was enhanced by an annealing treatment. A Ti/Al metal stack served as source and drain electrodes. Maximum drain current (I_D) exceeded 1 mA at a drain voltage (V_D) of 20 V. Electron mobility of the β-Ga₂O₃ channel was determined from maximum transconductance (g_m), as approximately, 1.39 ㎠/Vs. Reasonable device characteristics were demonstrated, from measurement of drain current-gate voltage, for mist-CVD-grown Ga₂O₃ thin films.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.352.1-352.1
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• 2014

Indium Tin Oxide (ITO) films are the most extensively studied and commonly used as ones of TCO films. The ITO films having a high electric conductivity and high transparency are easily fabricated on glass substrate at a substrate temperature over $250^{\circ}C$. However, glass substrates are somewhat heavy and brittle, whereas plastic substrates are lightweight, unbreakable, and so on. For these reasons, it has been recently suggested to use plastic substrates for flexible display application instead of glass. Many reaearchers have tried to produce high quality thin films at rood temperatures by using several methods. Therefore, amorphous ITO films excluding thermal process exhibit a decrease in electrical conductivity and optical transparency with time and a very poor chemical stability. However the amorphous Indium Gallium Zinc Oxide (IGZO) offers several advantages. For typical instance, unlike either crystalline or amorphous ITO, same and higher than a-IGZO resistivity is found when no reactive oxygen is added to the sputter chamber, this greatly simplifies the deposition. We reported on the characteristics of a-IGZO thin films were fabricated by RF-magnetron sputtering method on the PEN substrate at room temperature using 3inch sputtering targets different rate of Zn. The homogeneous and stable targets were prepared by calcine and sintering process. Furthermore, two types of IGZO TFT design, a- IGZO source/drain material in TFT and the other a- ITO source/drain material, have been fabricated for comparison with each other. The experimental results reveal that the a- IGZO source/drain electrode in IGZO TFT is shown to be superior TFT performances, compared with a- ITO source/drain electrode in IGZO TFT.

• 한국지반신소재학회논문집
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• 제12권1호
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• pp.29-38
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• 2013

본 논문에서는 생분해 배수재를 이용한 오염토양 정화기술의 현장적용성을 평가하기 위하여 생분해 배수재의 물리적 특성시험을 수행하였으며, 이를 이용한 현장실험을 통하여 중금속 오염토양의 정화효율을 분석하였다. 두 종류(실린더 코어형, 하모니카형)의 생분해 배수재에 대한 시험결과, 실린더 코어형 배수재의 경우, 한국산업규격 표준시방에서 제시하는 기준치를 모두 만족하였으며, 하모니카형 생분해성 배수재는 실린더 코어형 배수재에 비해 배수성능이 상당히 낮은 결과를 나타내었다. 또한 오염토양 복원시 사용한 세정제로는 자체독성이 적어 생태계에 미치는 영향을 최소화하며, 생물학적 재순환시스템과의 최적인 조건을 지니고 있는 시트르산(ctric acid)을 선정하여 중금속 중 Cd, Cu, Pb을 현장실험 대상 오염물질로 선정 후 실험을 수행하였다. 현장실험은 3가지 설치조건을 고려하여 정화효율을 분석하였으며, 반응물질이 도포된 생분해 배수재를 이용하여 세척제를 주입 추출을 동시에 수행한 경우가 복원효율이 가장 높은 것으로 평가되었다.