• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 영호남학술대회 논문집
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• pp.233-236
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• 2000

Polycrystalline Silicon Thin Film Transistors(Poly-Si TFT's), fabricated at temperature lower than $600^{\circ}C$ are now largely used in many applications, particularly in large area electrons. In this work, electrical stress effects on Poly-Si TFT's fabricated by Solid Phase Crystal(SPC) was investigated by measuring electric properities such as transfer and output characteristics, and channel conductance. Consequently, It is turned out that it should be noted the output characteristics, drain current and channel conductance, strongly degrade around origin.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1105-1108
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• 2003

In this paper, we have fabricated the hydrogenated n-channel polysilicon thin film transistor (TFT) with LDD structure and have analyzed the hot carrier degradation characteristics by electrical stress. We have compared the threshold voltage (Vth), sub-threshold slope (S), and trans-conductance (Gm) for devices with LDD (Lightly Doped Drain) structure and non-LDD at same active sizes. We have analyzed the hot carrier effects by the hydrogenation in devices. As a analyzed results, the threshold voltage, sub-threshold slope for n-channel poly-si TFT were increased, trans-conductance was decreased. The effects of hydrogenation in n-channel poly-si TFT with LDD structure were shown the lower variations of characteristics than devices of the non-LDD structure with nomal process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.182-188
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• 2006

An artificial neural network model for the microwave characteristics of an InGaAs/InP hemt for 70 nm gate length has been developed. The small-signal microwave parameters have been evaluated to determine the transconductance and drain-conductance. We have further investigated the frequency characteristics of the device. The neural network training have been done using the three layer architecture using Levenberg-Marqaurdt Backpropagation algorithm. The results have been compared with the experimental data, which shows a close agreement and the validity of our proposed model.

• 한국정보통신학회논문지
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• 제17권8호
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• pp.1885-1890
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• 2013

본 연구에서는 극저온에서 다중 게이트 구조인 나노스케일 p-채널 무접합(junctionless) 과 축적모드(accumulation mode) 다중 게이트 FET의 전기적 특성을 분석하였다. 헬륨을 사용하는 극저온 프로브 스테이션을 사용하여 소자를 측정하였다. 극저온과 낮은 드레인 전압에서 무접합 트랜지스터의 드레인 전류의 진동 현상이 축적모드 보다 심한 것을 알 수 있었다. 이는 무접합 트랜지스터에서는 채널이 실리콘 박막의 가운데 형성되므로 전기적 채널 폭이 축적모드 트랜지스터 보다 작기 때문이다. 온도가 증가할수록 드레인 전류가 증가하며 최대 전달 컨덕턴스도 증가하는 것을 알 수 있었다. 이는 온도가 증가할수록 문턱전압이 감소하며 이동도가 증가하는 데서 기인된 것을 알 수 있었다. 소자의 크기가 나노미터 레벨로 축소되면 양자현상에 의한 드레인 전류 진동이 상온에도 일어날 수 있다.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.423-430
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating $n^{+}$ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating $n^{+}$ zones, the transistor channel region is split into four zones with different lengths defined by a floating $n^{+}$ region. This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA while that of the conventional dual-gate structure is 0.5 mA at a 12 V drain voltage and a 7 V gate voltage. This results show a $80 {\%}$ enhancement in on-current by adding two floating $n^{+}$ zones. Moreover we observed the reduction of electric field In the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• Transactions on Electrical and Electronic Materials
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• 제16권5호
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.130-133
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• 2010

This paper presents a study of the influence of variation of counter doping thickness on short channel effect in symmetric double-gate (DG) nano MOSFETs. Short channel effects are estimated from the computed values of current-voltage (I-V) characteristics. Two dimensional Quantum transport equations and Poisson equations are used to compute DG MOSFET characteristics. We found that the transconductance ($g_m$) and the drain conductance ($g_d$) increase with an increase in p-type counter-doping thickness ($T_c$). Very high value of transconductance ($g_m=38\;mS/{\mu}m$) is observed at 2.2 nm channel thickness. We have established that the threshold voltage of DG MOSFETs can be tuned by selecting the thickness of counter-doping in such device.

• 한국전기전자재료학회논문지
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• 제11권5호
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• pp.347-352
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• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.679-682
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• 2005

Negative-differential conductance (NDC) characteristics as well as negative-differential trans-conductance (NDT) characteristics have been observed in the room temperature I-V characteristics of Field-induced Inter-band Tunneling Effect Transistors (FITETs). These characteristics have been explained with inter-band tunneling physics, from which, inter-band tunneling current flows when the energy bands of degenerately doped regions align, and it does not flow when they don't. FITET is an SOI device and the body region is not directly connected to the external terminal. Therefore, Fermi energy in the body region is determined by electrical coupling among four regions - gate, source, drain and substrate. So, a quasi Fermi energy of the majority carriers in the floating body region can be changed by external voltages, and this causes the energy band movements in the body region, which determine whether the energy bands between degenerately doped junctions aligns or not. This is a key point for an explanation of NDT and NDC characteristics. In this paper, a quasi Fermi energy movement in the floating body region of FITET was investigated by a device simulation. This result was applied for the description of relation between quasi Fermi energy in the body region and external gate bias voltage.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 추계학술대회
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• pp.773-776
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• 2014

본 연구에서는 채널 길이와 폭의 변화에 따른 실리콘 나노와이어 MOSFET 소자의 아날로그 특성을 비교 분석 하였다. 측정 온도는 $30^{\circ}C$, $50^{\circ}C$, $75^{\circ}C$, $100^{\circ}C$이다. 사용된 소자의 폭은 20nm, 30nm, 80nm, 130nm 와 길이는 250nm, 300nm, 250nm, 500nm을 사용하였다. 소자의 아날로그 특성은 이동도, 트랜스컨덕턴스, Early 전압, 전압이득, 드레인 전류 이다. 이동도는 폭이 증가함에 따라 증가하고 길이와 온도가 증가할수록 감소한다. 트랜스 컨덕턴스는 폭이 증가하면 증가한다. Early 전압은 길이와 온도가 증가함에 따라 증가하고 폭이 증가함에 따라 감소한다. 따라서 이득은 폭의 감소와 길이가 증가함에 따라 증가하고 온도가 증가함에 따라 감소하는 것을 알 수 있었다.