• E2M - 전기 전자와 첨단 소재
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• 제8권5호
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• 전기의세계
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• 제30권10호
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• pp.645-654
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• 1981

A technique has been proposed for fabricating a submicron channel vertical V-groove JFET using standard photolithography. A finite element numerical simulation of the V-groove JFET operation was performed using a FORTRAN progrma run on a Cyber-174 computer. The numerical simulation predicts pentode like common source output characteristics for the p$^{+}$n Vertical V-groove JFET with maximum transconductance representing approximately 6 precent of the zero bias drain conductance value and markedly high drain conductance at large drain voltages. An increase in the acceptor concentration of the V-groove JFET gate was observed to cause a significant increase in the transconductance of the device. Therefore, as above mentioned, this paper is study on the analysis of a Vertical V-groove Junction Field Effect Transistor with Finite Element Method.d.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 춘계학술대회 논문집
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• pp.86-89
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• 1995

In this pacer, The effect of the impedances in SNOSEFT s memory devices has been developed. The effect of source and drain impedances are measuring using the method of the field effect bias resistance in the inner resistance regions of the device structure and external bias resistance. The effect of impedance by source and drain resistance shows according to increasing to the storage of memory charges, shows according to a function of decreasing to the gate voltages, shows the delay of threshold voltages, The delay time of low conductance state and high conductance state by the impedance effect shows 3 [${\mu}$sec] and 1[${\mu}$sec] respectively.

• 대한전자공학회논문지
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• 제24권5호
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• pp.794-803
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• 1987

In this paper, the SPICE 2.G6 JFET subroutine and other related subroutines are modified for circuit simulation of GaAs MESFET IC's. The hyperbolic tangent model is used for the drain current-voltage characteristics of GaAs MESFET's and derived channel-conductance and drain-conductance model from the above current model are implemented into small-signal model of GaAs MESFET's. And, device capacitance model which consider after-pinch-off state are modified, and device charge model for SPICE 2G.6 are proposed. The result of modification is shown to be suitable for GaAs circuit simulator, showing good agreement with experimetal results. Forthermore the DC convergence of this paper is better than that of SPICE 2.G JFET subroutine. GaAs MESFET model in this paper is applied for both depletion mode GaAs MESFET and enhancement-mode GaAs MESFET without difficulty.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• 대한전자공학회논문지SD
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• 제49권4호
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• pp.1-6
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• 2012

본 논문에서는 고주파에서 동작하는 터널링 전계효과 트랜지스터 (TFET)의 소신호 파라미터 추출과 이에 대한 분석을 다루고 있다. 시뮬레이션으로 구현된 TFET의 채널 길이는 50 nm에서 100 nm 사이에서 변화되었다. Conventional planar MOSFET 기반의 quasi-static 모델을 이용하여 TFET의 파라미터 추출이 이루어졌으며 다른 채널 길이를 갖는 TFET에 대한 소신호 파라미터의 값을 게이트 바이어스 변화에 따라서 추출하였다. 추출 결과로부터 effective gate resistance와 transconductance, source-drain conductance, gate capacitance 등 주요 파라미터의 채널 길이 변화에 따른 경향성이 conventional MOSFET과 상당히 다른 것을 확인하였다. 그리고 $f_T$는 MOSFET과 달리 게이트 길이 역수의 값에 정확히 반비례하는 특성을 보였으며 TFET의 고주파 특성 향상을 transconductance의 개선이 아닌 gate capacitance의 감소에 의하여 가능함을 알 수 있었다.

• 한국전기전자재료학회논문지
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• 제26권8호
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• pp.582-586
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• 2013

In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• 한국통신학회논문지
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• 제24권10A호
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• pp.1579-1587
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• 1999

게이트 길이가 $0.2\mu\textrm{m}$인 P-HEMT에 대하여 드레인 바이어스 전류의 변화 및 게이트 폭에 대해 스케일링이 가능한 잡음모델을 제안하였다. 본 논문에서는 S-파라미터를 정확히 예측하기 위하여 $\tau$를 제외한 intrinsic 파라미터는 offset를 도입하여 정규화 한 후 스케일링을 하였다. 드레인 포화전류에 대한 드레인 전류의 비율과 게이트 폭을 변수로 하는 소신호 모델 파라미터의 맞춤함수를 구하였다. 또한, 잡음 파라미터를 정확히 예측하기 위하여 진성저항 잡음 온도 $\textrm{T}_{g}$, 게이트 단 전류 잡음원 등가잡음 컨덕턴스 $\textrm{G}_{ni}$, 드레인 단 전류와 게이트 폭에 거의 관계없으며 이의 평균값은 주변온도와 유사한 값으로 $\textrm{G}_{ni}$는 회로 특성에 영향을 미치지 않을 정도로 작은 값으로 추출되었다. 그러므로, $\textrm{G}_{no}$만을 잡음 모델정수로 하는 잡음모델과 $\textrm{T}_{g}$, $\textrm{G}_{ni}$, $\textrm{G}_{no}$를 잡음 모델정수로 하는 잡음모델을 측정값과 비교하여 본 결과 Gno만을 갖는 잡음모델도 측정된 잡음 파라미터와 잘 일치하였다. 따라서, 모델 정수추출이 간단한 $\textrm{G}_{no}$만을 갖는 잡음모델은 게이트 폭과 바이어스 전류에 대해 스케일링이 가능한 실용적인 잡음모델임을 확인하였다.

• 한국컴퓨터산업학회논문지
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• 제6권5호
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• pp.783-790
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating n+ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region, This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9mA while that of the conventional dual-gate structure is 0.5mA at a 12V drain voltage and a 7V gate voltage. This result shows a 80% enhancement in on-current. Moreover we observed the reduction of electric field in the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition, we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.