• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.41-44
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• 2004

The trend of decreasing the minimal structure sizes in microelectronics is still being continued. Therefore in its roadmap the Semiconductor Industries Association predicts a printed minimum MOS-transistor channel length of 10 nm for the year 2018. Although the resolution of optical lithography still dramatically increases, there are known and proved solutions for structure sizes significantly below 50 nm up to now. In this work a new method for the fabrication of extremely small MOS-transistors with a channel length and width below 50 nm with low demands to the used lithography will be explained. It's a further development of our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, with a scaling of the transistor's width. The used technique is proved in a first charge of MOS-transistors with a channel area of W=200 nm and L=80 nm. The full CMOS compatible technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size. The electrical characteristics of such small transistor will be analyzed and the ultimate limits of the technique will be discussed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.57-65
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• 1995

The effects of device geometry and layout on high speed performance such as current gain outoff frequency(f$_{T}$) and maximum oscillation frequency(f$_{max}$) are of very improtant for the scaling-down of geterojunction bipolar transistors(HBT$_{s}$). In this paper AlGaAs/GaAs HBTs are fabricated by MBE epitaxial growth and conventional mesa process, and the experimental data of emitter-base geometru dependency of HBT performance are presented in order to provide the quantitative information for optimum device structure design. It is shown that f$_{T}$ and f$_{max}$ are inversely proportional to the emiter stripe width, while the low emitter perimeter/area ratio is better to f$_{T}$ and worse ot f$_{max}$. It is also demonstrated the f$_{T}$ and f$_{max}$ are highly improved by the emitter-base spacing reduction resulting in less parsitic effects. As the result f$_{T}$ of 42GHz and f$_{max}$ of 23GHz are obtained for fabricated HBT with emitter area of 3${\times}20^{\mu}m^{2}$ and E-B spacing of 0.2$\mu$m.m.m.

• Journal of Magnetics
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• v.8 no.1
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• pp.24-31
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• 2003

The discoveries of antiferromagnetic coupling in Fe/Cr multilayers by Grunberg, the Giant Magneto Resistance by Fert and Grunberg and a large tunneling magnetoresistance at room temperature by Moodera have triggered enormous research on magnetic thin films and magnetoelectronic devices. Large opportunities are especially opened by the spin dependent tunneling resistance, where a strong dependence of the tunneling current on an external magnetic field can be found. We will briefly address important basic properties of these junctions like thermal, magnetic and dielectric stability and discuss scaling issues down to junction sizes below 0.01 $\mu\textrm{m}$$^2$with respect to single domain behavior, switching properties and edge coupling effects. The second part will give an overview on applications beyond the use of the tunneling elements as storage cells in MRAMs. This concerns mainly field programmable logic circuits, where we demonstrate the clocked operation of a programmed AND gate. The second 'unconventional' feature is the use as sensing elements in DNA or protein biochips, where molecules marked magnetically with commercial beads can be detected via the dipole stray field in a highly sensitive and relatively simple way.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.1-6
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• 2013

3D integrated circuit(IC) technology with TSV(through Si via) liquid cooling system is discussed. As a device scales down, both interconnect and packaging technologies are not fast enough to follow transistor's technology. 3D IC technology is considered as one of key technologies to resolve a device scaling issue between transistor and packaging. However, despite of many advantages, 3D IC technology suffers from power delivery, thermal management, manufacturing yield, and device test. Especially for high density and high performance devices, power density increases significantly and it results in a major thermal problem in stacked ICs. In this paper, the recent studies of TSV liquid cooling system has been reviewed as one of device cooling methods for the next generation thermal management.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.581-582
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• 2006

In this paper, we investigate three different types of multi-fingered layout nMOSFET devices with varying $W_f$(unit finger width) and $N_f$(number of finger). Using layout modification, we improve $f_T$(current gain cutoff frequency) value of 15GHz without scaling down, and moreover, we decrease $NF_{min}$(minimum noise figure) by 0.23dB at 5GHz. The RF noise can be reduced by increasing $f_T$, choosing proper finger width, and reducing the gate resistance. For the same total gate width using multi-fingered layout, the increase of finger width shows high $f_T$ due to the reduced parasitic capacitance. However, this does not result in low $NF_{min}$ since the gate resistance generating high thermal noise becomes larger under wider finger width. We can obtain good RF characteristics for MOSFETs by using a layout optimization technique.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.1
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• pp.23-32
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• 2011

In this paper, we develop a method for generating thumbnail images at hybrid domain combined the spatial domain and transform domain. The proposed method generates a pixel of a thumbnail image by adding a DC value of residual transform coefficients and an average value of an estimate block. For effectively calculating average values of estimate blocks, we propose a method for reconstructing the boundary pixels of a block. In comparison to the conventional method of decoding the bit stream then scaling down the decoded images, the developed method reduces the complexity by more than 60% while producing identical thumbnail images.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.52-62
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• 2008

In this paper, we develop a method that changes the resolutions of images in an arbitrary block transform domain by using a filter that suits to the characteristics of the underlying images. To accomplish this, we represent each procedure resizing images in an arbitrary transform domain as matrix multiplications and we derive the matrix that scales the image resolutions from the matrix multiplications. The resolution scaling matrix is also designed to be able to select the up/down-sampling filter that suits the characteristics of the image. Experiments show that the proposed method produces the reliable performances when it is applied to various transforms and to images that are mixed with predicted and non-predicted blocks which are generated during video coding.

• Journal of Korean Academy of Nursing Administration
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• v.20 no.4
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• pp.394-404
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• 2014

Purpose: The purpose of this study was to identify the conceptual structure of stressors experienced by nursing students during clinical practice. Methods: Ten men and 10 women nursing college students were interviewed. The results were 208 ideas. By synthesizing and editing these ideas, the final statement was trimmed down to 39 questions. The next step was to have the participants classify these 39 final questions. They were asked to rate stress scores using a five-point scale. Through multidimensional scaling analysis and hierarchical cluster analysis yielded dimensions and clusters. Results: Results of the study showed 2 dimensions which were classified as 'interpersonal relationship-practice system' and 'identity-practice environment'. It also yielded 8 clusters which were classified as 'role confusion', 'gender discrimination', 'attitudes of medical personnel and patients', 'comparison between fellow students', 'difference between theory and practice', 'disestablishing the role of practice guide', 'interference with training', and 'problems of the practice environment'. Further, stress factors and stress levels were differentiated depending on the gender of the student. Conclusion: The results of the study indicate that educators who are developing clinical practice programs and clinical practitioners should consider stressors during clinical practice and the educational implications to nursing students.