• 전자공학회논문지A
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• 제33A권11호
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• pp.140-151
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• 1996

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

• 대한전자공학회논문지
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• 제22권3호
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• pp.68-76
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• 1985

전하 결함 소자를 이용한 16×16 이차원 영상 감지 소자가 제작되었다. 제작된 소자는 2상(two-Phase)의 전극 구조로 제작 되었고 프레임 이동(frame transfer) 방식으로 동작한다. 표면 전위차를 얻기위해 이온 주입을 했고 NMOS공정을 따라 제작되었다. 영상을 얻기위한 시스템은 광학 렌즈 클럭 발생 및 구동 회로, 계단형 신호 발생기로 이루어지는데, EPROM을 사용하여 클럭 발생회로를 간단하게 하였다. 영상 시스템을 사용하여 오실로스코프 화면에 알파베트를 표시할 수 있었다. 소자의 특성으로 전하 이동 손실률과 암전류를 측정하였다.

• 대한전자공학회논문지SD
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• 제44권7호통권361호
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• pp.16-23
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• 2007

본 논문에서는 완전 공핍된 SOI형 대칭 이중게이트 MOSFET의 문턱 전압에 대한 간단한 해석적 모델을 제시하고자 실리콘 몸체 내의 전위 분포를 근사적으로 채널에 수직한 방향의 좌표에 대해 4차 다항식으로 가정하였다. 이로써 2차원 포아송 방정식을 풀어 표면 전위의 표현식을 도출하고, 이 결과로부터 드레인 전압 변화에 의한 문턱 전압의 roll-off를 비교적 정확하게 기술할 수 있는 문턱 전압의 표현식을 closed-form의 간단한 표현식으로 도출하였다. 도출된 표현식으로 모의 실험을 수행한 결과 $0.01\;[{\mu}m]$의 실리콘 채널 길이 범위까지 채널 길이에 지수적으로 감소하는 것을 보이는 비교적 정확한 결과를 얻을 수 있음을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.40-50
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• 2011

A two-dimensional (2D) analytical model for the potential distribution and threshold voltage of short-channel ion-implanted GaAs MESFETs operating in the sub-threshold regime has been presented. A double-integrable Gaussian-like function has been assumed as the doping distribution profile in the vertical direction of the channel. The Schottky gate has been assumed to be semi-transparent through which optical radiation is coupled into the device. The 2D potential distribution in the channel of the short-channel device has been obtained by solving the 2D Poisson's equation by using suitable boundary conditions. The effects of excess carrier generation due to the incident optical radiation in channel region have been included in the Poisson's equation to study the optical effects on the device. The potential function has been utilized to model the threshold voltage of the device under dark and illuminated conditions. The proposed model has been verified by comparing the theoretically predicted results with simulated data obtained by using the commercially available $ATLAS^{TM}$ 2D device simulator.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.161-165
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• 2023

This paper designed a voltage feedback driving circuit to compensate for the characteristic deviation of the Active Matrix Organic Light Emitting Diode driving Thin Film Transistor. This paper describes a stable and fast circuit by applying charge sharing and polar stabilization methods. A 12-inch Organic Light Emitting Diode with a Double Wide Ultra eXtended Graphics Array resolution creates a screen distortion problem for line parasitism, and charge sharing and polar stabilization structures were applied to solve the problem. By applying Charge Sharing, all data lines are shorted at the same time and quickly positioned as the average voltage to advance the compensated change time of the gate voltage in the next operation period. A buffer circuit and a current pass circuit were added to lower the Amplifier resistance connected to the line as a polar stabilization method. The advantage of suppressing the Ringing of the driving Thin Film Transistor can be obtained by increasing the stability. As a result, a circuit was designed to supply a stable current to the Organic Light Emitting Diode even if the characteristic deviation of the driving Thin Film Transistor occurs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.210-215
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• 2017

We have developed the neuromorphic system that can work with the four-terminal Si-based synaptic devices and verified the operation of the system using simulation tool and printed-circuit-board (PCB). The symmetrical current mirrors connected to the n-channel and p-channel synaptic devices constitute the synaptic integration part to express the excitation and the inhibition mechanism of neurons, respectively. The number and the weight of the synaptic devices affect the amount of the current reproduced from the current mirror. The double-stage inverters controlling delay time and the NMOS with large threshold voltage ($V_T$) constitute the action-potential generation part. The generated action-potential is transmitted to next neuron and simultaneously returned to the back gate of the synaptic device for changing its weight based on spike-timing-dependent-plasticity (STDP).

• 건축역사연구
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• 제20권6호
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• pp.169-184
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• 2011

The following research of the road network of Jeju-Eupseong during Daehan Empire period has a twofold purpose: to study some characteristics of the road network at that time; and, to restore it to the original form of that period before a newly constructed road, called Shinjakro, has been established. As an attempt to trace the old shape of Jeju-Eupseong, this study analyzed some historical factors based on the first land cadastral map which was made in 1914, including outskirts of Jeju-Eupseong; such as castle itself, castle gate, road, bridge, lots of land, etc. Then this study also tried to restore the old road network of Jeju-Eupseong, through finding the original land-lot shape in the land cadastral map. There was five Shinjakro made between 1914 and 1917. The road network before then was composed of the double east-west axes and the single north-south axis. These axes was connected to some important place of the inside of Jeju-Eupseong; such as castle gates, fountains, Gaek-sa, etc. There were many branch lines between these main axes at about 80-120m intervals. Also there was an outer road along the outer wall of castle, connected with each castle gates. Especially, the north-west axis was the baseline which divided into two large parts, a government office area and non-government area (housing and commercial street for the people). Finally, this paper examines that the road network of Jeju-Eupseong was the true result for the efficient function of the city, especially considering natural geographical conditions and environment of living of that time.

• 한국항행학회논문지
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• 제20권5호
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• pp.453-461
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• 2016

최근 다양한 센서를 활용하는 응용분야의 증가로 인해 가변전송률을 지원하는 무선 통신 시스템의 필요성이 증가하고 있다. 이에 IEEE 802.15.4 ZigBee 시스템을 개량하여 250 kbps이하의 다양한 가변전송률을 지원하는 AZB (advanced ZigBee) 시스템이 제안 되었다. AZB 시스템은 250 kbps 이하 125 kbps, 62.5 kbps, 31.25 kbps의 가변 전송률을 지원할 수 있는 프리앰블 구조를 정의하였는데, 정의된 프리앰블 구조로 인해 AZB 시스템의 시간동기부의 회로 면적이 급격히 증가하는 문제점이 발생한다. 이에, 본 논문에서는 가변 전송률을 지원하면서도 시간동기부의 회로면적을 감소시킬 수 있는 새로운 프리앰블 구조 및 시간 동기 획득 알고리즘을 제안한다. 제안된 시간 동기부는 6.92 k의 FPGA (field programmable gate array) logic slices 합성되었고, 기존 구조 대비 62.3 % 복잡도 감소를 보였다.

• 한국패류학회지
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• 제28권3호
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• pp.277-291
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• 2012

Aquaculture is challenged by a number of constraints with future efforts towards sustainable production. Global climate change has a potential damage to the sustainability by changing environmental surroundings unfavorably. The damaging parameters identified are water temperature, sea level, surface physical energy, precipitation, solar radiation, ocean acidification, and so on. Of them, temperature, mostly temperature elevation, occupies significant concern among marine ecologists and aquaculturists. Ocean acidification particularly draws shellfish aquaculturists' attention as it alters the marine chemistry, shifting the equilibrium towards more dissolved CO2 and hydrogen ions ($H^+$) and thus influencing signaling pathways on shell formation, immune system, and other biological processes. Temperature elevation by climate change is of double-sidedness: it can be an opportunistic parameter besides being a generally known damaging parameter in aquaculture. It can provide better environments for faster and longer growth for aquaculture species. It is also somehow advantageous for alleviation of aquaculture expansion pressure in a given location by opening a gate for new species and aquaculture zone expansion northward in the northern hemisphere, otherwise unavailable due to temperature limit. But in the science of climate change, the ways of influence on aquaculture are complex and ambiguous, and hence are still hard to identify and quantify. At the same time considerable parts of our knowledge on climate change effects on aquaculture are from the estimates from data of fisheries and agriculture. The consequences may be different from what they really are, particularly in the temperature region. In reality, bivalves and tunicates hung or caged in the longline system are often exposed to temperatures higher than those they encounter in nature, locally driving the farmed shellfish into an upper tolerable temperature extreme. We review recent climate change and following environment changes which can be factors or potential factors affecting shellfish aquaculture production in the temperate region.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 추계학술대회
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• pp.737-739
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• 2010

본 연구에서는 MicroTec4.0을 이용하여 더블게이트 MOSFET의 문턱전압이하특성을 채널두께의 변화에 따라 분석하였다. 소자의 고집적을 위한 특성분석 기술은 빠른 변화를 보이고 있다. 이에 따라 고집적 소자의 특성을 시뮬레이션을 통하여 이해하고 이에 맞게 제작하는 기술은 매우 중요한 과제 중의 하나가 되었다. 더블게이트 MOSFET에서 산화막 두께와 채널 두께는 문턱전압의 크기를 결정하며 Ss(Subthreshold swing)에 커다란 영향을 미친다. 본 연구에서는 채널의 두께를 1nm에서 3nm까지 변화시켜 채널 두께에 따른 문턱전압과 Ss(Subthreshold swing)를 조사하였다.