• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.4
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• pp.385-390
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• 2023

In this paper, the 1,700 V level SiC-based power MOSFET device widely used in electric vehicles and new energy industries was designed, that is, a single trench gate power MOSFET structure and a double trench gate power MOSFET structure were proposed to analyze electrical characteristics while changing the design and process parameters. As a result of comparing and analyzing the two structures, it can be seen that the double trench gate structure shows quite excellent characteristics according to the concentration of the drift layer, and the breakdown voltage characteristics according to the depth of the drift layer also show excellent characteristics of 200 V or more. Among them, the trench gate power MOSFET device can be applied not only to the 1,700 V class but also to a voltage range above it, and it is believed that it can replace all Si devices currently applied to electric vehicles and new energy industries.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.799-804
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• 2016

To analyze the phenomenon of drain induced barrier lowering(DIBL) for top and bottom gate oxide thickness of asymmetric double gate MOSFET, the deviation of threshold voltage is investigated for drain voltage to have an effect on barrier height. The asymmetric double gate MOSFET has the characteristic to be able to fabricate differently top and bottom gate oxide thickness. DIBL is, therefore, analyzed for the change of top and bottom gate oxide thickness in this study, using the analytical potential distribution derived from Poisson equation. As a results, DIBL is greatly influenced by top and bottom gate oxide thickness. DIBL is linearly decreased in case top and bottom gate oxide thickness become smaller. The relation of channel length and DIBL is nonlinear. Top gate oxide thickness more influenced on DIBL than bottom gate oxide thickness in the case of high doping concentration in channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.500-510
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• 2013

In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.15-22
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• 2008

The bulk-planer MOSFET has a scaling limitation due to the short channel effect (SCE). The Double-Gate MOSFET (DG-MOSFET) is a next generation device for nanoscale with excellent control of SCE. The quantum effect in lateral direction is important for subthreshold characteristics when the effective channel length of DG-MOSFET is less than 10nm, Also, ballistic transport is setting important. This study shows modeling and design issues of nanoscale DG-MOSFET considering the 2D quantum effect and ballistic transport. We have optimized device characteristics of DG-MOSFET using a proper value of $t_{si}$ underlap and lateral doping gradient.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.127-138
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• 2013

The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of $VIP_2$ and $VIP_3$. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.331-341
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• 2013

In the present work, the effect of the gate-to-drain capacitance ($C_{gd}$) on the noise performance of a symmetric tied-gate $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ double-gate HEMT is studied using an accurate charge control based approach. An analytical expression for the gate-to-drain capacitance is obtained. In terms of the intrinsic noise sources and the admittance parameters ($Y_{11}$ and $Y_{21}$ which are obtained incorporating the effect of $C_{gd}$), the various noise performance parameters including the Minimum noise figure and the Minimum Noise Temperature are evaluated. The inclusion of gate-to-drain capacitance is observed to cause significant reduction in the Minimum Noise figure and Minimum Noise Temperature especially at low values of drain voltage, thereby, predicting better noise performance for the device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1749-1753
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• 2005

In this paper, we have investigated electrical characteristics by action temperature of double gate structure that have main gate and side gate. Could know current-voltage characteristic is superior in ultra low temperature (77 K) as well as in room temperature (300 K). Also, conditions of most suitable for get superior DG MOSFET's dynamic characteristics are main gate length of 50nm and side gate length of 70nm and could know that should be approved more than voltage 2V. Also, this DG MOSFET usefully use may as digital device because on-off characteristic is superior.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.192-198
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• 2017

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage ($V_{amb}$) and double gate structure is applied to improve on-current ($I_{ON}$) and subthreshold swing (SS). We discussed the fin width ($W_S$), body doping concentration, sidewall width ($W_{side}$), drain and gate underlap distance ($X_d$), source doping distance ($X_S$) and pocket doping length ($X_P$) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high $I_{ON}$ of $1.2{\times}10^{-3}A/{\mu}m$ and low $V_{amb}$ of -2.0 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• Journal of electromagnetic engineering and science
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• v.2 no.1
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• pp.56-58
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• 2002

In this paper, the double conversion gate mixer using a half-LO frequency is described at 25 GHz band. The proposed mixer uses two HEMTs excited by a single LO signal of half-LO frequency in order to generate the second IF signal. That is, the LO signal having the half-LO frequency is only fed into the gate of the first HEMT mixer as a normal gate mixer. The LO signal through the first mixer is find into the second mixer The proposed miler requires not only half of the normal LO frequency, but also lower LO power than the conventional subharmonically pumped milers. Over the bandwidth of 500 MHz at 24.5 GHz, the conversion gain is 2.5 dB, the noise figure is 9 dB, and the isolation between RF and LO port is 32 dB when the LO poller is 0 dBm at 12.65 GHz.