• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.9
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• pp.1493-1496
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• 2016

This paper proposes a system for reducing the standby power consumption in using the consumer electronic devices such as a television, a home theater, a set-top box, or a DVD player. The system is consisted of a flyback converter, monitoring circuits, a relay and a micro-processor. The proposed system can reduce the standby power consumption by disconnecting the AC input and the consumer devices can be turned on with a remote control. The proposed standby power system consumes the low power to receive the infrared signal from the remote controller. Furthermore, a electronic double layer capacitor is used to store the energy with high efficiency. The proposed power system can operate the 플라이백 converter to charge the electronic double layer capacitor and connect the AC input to the consumer electronic devices. The proposed power circuit can reduce the standby power consumption in AV devices without increasing the cost. The prototype is implemented to verify the system with the commercialized products.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.8
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• pp.1207-1211
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• 2015

Various laser systems have been widely used in almost all industrial technologies because they have high energy density, directivity and coherence. Recently the clinical application is becoming wider in medical parts such as incurable disease, diagnosis and so on. Generally, ruby laser beam has the greatest efficacy for removing tattoos, freckle and other skin problem. But current medical ruby laser system has the maximum repetition rate of 2Hz and optical output beam energy of 1J. Many medical doctors really want to have a high repetition ruby laser system because that can reduce the operation time. We investigated a new ruby laser system with high repetition rate of 4Hz using double cavities. Furthermore, we develop a new power supply system adopting zero voltage switching(ZVS) to minimize switching loss by LLC resonant converter designed as 2kW class.

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.921-930
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• 2016

This paper proposes a design and control method for a high-voltage direction current modular multilevel converter (HVDC-MMC) considering the capacitor voltage ripple of the submodule (SM). The capacitor voltage ripple consists of the line frequency and double-line-frequency components. The double line- frequency component does not fluctuate according to the active power, whereas the line-frequency component is highly influenced by the grid-side voltage and current. If the grid voltage drops, a conventional converter increases the current to maintain the active power. A grid voltage drops, current increment, or both occur with a capacitor voltage ripple higher than the limit value. In order to reliably control an MMC within a limit value, the SM capacitor should be designed on the basis of the capacitor voltage ripple. In this paper, the capacitor voltage ripple according to the grid voltage and current are analyzed, and the proposed control method includes a current limitation method considering the capacitor voltage ripple. The proposed design and control method are verified through simulation using PSCAD/EMTDC.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.231-238
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• 2013

This paper describes a DC-DC converter IC for Flat Panel Displays. In case of operate LCD devices various type of DC supply voltage is needed. This device can convert DC voltage from 6~14[V] single supply to -5[V], 15[V], 23[V], and 3.3[V] DC supplies. In order to meet current and voltage specification considered different type of DC-DC converter circuits. In this work a negative charge pump DC-DC converter(-5V), a positive charge pump DC-DC converter(15V), a switching Type Boost DC-DC converter(23V) and a buck DC-DC converter(3.3V). And a oscillator, a thermal shut down circuit, level shift circuits, a bandgap reference circuits are designed. This device has been designed in a 0.35[${\mu}m$] triple-well, double poly, double metal 30[V] CMOS process. The designed circuit is simulated and this one chip product could be applicable for flat panel displays.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.10
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• pp.1474-1480
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• 2017

This paper presents a new LED current balancing scheme using double-step-down dc-dc converter. With the proposed structure, the two channel LED currents are automatically balanced without using any dedicated control or auxiliary circuit. In addition, switching loss of the switching devices in the proposed LED driver is lower than that of the conventional buck LED driver. To verify the operation of the proposed LED driver, a hardware prototype is built and tested with different number of LED.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.395-398
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• 2002

This paper presents generalized small-signal models for complementary driven double-ended isolated converters. The proposed small-signal models include the effect of the parasitic resistances, which have dominant influence on the damping of the secondary Power stage double-pole. To confirm the validity of the new models, an asymmetrical half-bridge converter with confer-taped rectifier and a forward-flyback converter with current doubler rectifier were built, and their performance were compared with the theoretical prediction.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.325-329
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• 2011

This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1401-1403
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• 2005

This paper presents generalized small-signal models for asymmetrically-driven double-ended dc-to-dc converters. The proposed small-signal models include the effects of the parasitic resistances, which have dominant influence on the damping of the secondary power stage double-pole. To confirm the validity of new models, an asymmetrical half-bridge converter with center-taped rectifier and a forward-flyback converter with current doubler rectifier were built, and their performances were compared with the theoretical predictions.

• Journal of Electrical Engineering and Technology
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• v.6 no.4
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• pp.505-512
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• 2011

A novel passive boost power converter forsingle-phaseswitched reluctance motor is presented. A simple passive circuit is proposed comprisingthree diodes and one capacitor. The passive circuitis added in the front-end of a conventional asymmetric converter to obtain high negative bias. Based on this passive network, the terminal voltage of the converter side is a general DC-link voltage level in parallel mode up to a double DC-link voltage level in series mode. Thus,it can suppress the negative torque generation from the tail current and improve the output power. The results of the comparative simulation and experiments forthe conventional and proposed converter verify the performance of the proposed converter.