• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.599-603
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• 1988

In this paper, a flash type A/D converter using Variable Threshold Logic circuit is designed and is layonted by double metal CMOS 2 um design rule. Comparator and register string which is the basic elements of a general flash type A/D converter are substituted by simple comparator circuit which is slightly modified from cmos inverter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.546-548
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• 2005

This paper proposes a unity power factor ZVT PWM single-phase rectifier. The ZVT soft switching are achieved by using a simple ZVT circuit, and the reduced conduction losses are achieved by employing a single-stage converter, instead of a typical double-stage converter composed of front end diode rectifier and cascaded boost rectifier. Furthermore, thanks to good features such as simple PWM control at constant frequency, low switch stress and low VAR rating of commutation circuits, it is suitable for high power applications. The principle of operation is explained in detail, and simulation results of the new converter are also included.

• Journal of international Conference on Electrical Machines and Systems
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• 제2권2호
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• pp.246-253
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• 2013

The Modular Multilevel Converter (MMC) with full bridge cells is available for utility interactive inverter in high voltage line. When it is interconnected with power line, it is possible to control the active power flow in order to supply or charge the power in the line. This research applied the MMC to grid connection system of distributed generator and a power flow control for the MMC is investigated. Theory of power flow between the MMC and the power line is described and control method of power flow and capacitor voltages on arm cells for the MMC are proposed. And effectiveness of the proposed control method is presented by simulation.

• Journal of Power Electronics
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• 제14권4호
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• pp.778-787
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• 2014

This study presents an input filter resonance mitigation method for an AC-DC matrix converter. This method combines the advantages of the one-cycle control strategy and the active damping technique. Unnecessary sensors are removed, and system cost is reduced by employing the grid-side input currents as feedback to damp out LC resonance. A model that includes the proposed method and the input filter is established with consideration of the delay caused by the actual controller. A zero-pole map is employed to analyze model stability and to investigate virtual resistor parameter design principles. Based on a double closed-loop control scheme, the one-cycle control strategy does not require any complex modulation index control. Thus, this strategy can be more easily implemented than traditional space vector-based methods. Experimental results demonstrate the veracity of theoretical analysis and the feasibility of the proposed approach.

• Journal of the Optical Society of Korea
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• 제6권2호
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• pp.48-54
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• 2002

Experimental study is performed on flashlamp-pumped Ti: sapphire lasers with single, double, and four-partial-ellipse-pump cavities aiming at improving the performance of the lasers. The output energy of 604 mJ per pulse with a width of 25 $\mu$s at a total laser efficiency of 0.13% is achieved in the laser pumped by a light pulse of 45$\mu$s without a fluorescent converter The laser output energy versus its Ti: sappy ire rod length, pumping-light pulse duration, and electrical input energy are discussed with or without using a fluorescent converter. The result shows that much more output energy is obtained il a longer Ti: sapphire-rod laser pumped by a shorter light pulse when its output coupler has an optimized transmittance. In addition, an enhancement of output energy by a factor of 7 is achieved. in the laser using a fluorescent converter LD490.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.630-637
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• 2003

In this paper, a DBM(double balanced mixer) of 2 GHz is implemented on FR4(h=1.6mm, ${\epsilon}_r=4.6$) substrate. The structure of double balanced mixer requires, in general, two talons and a quad diode. For balun, a novel planar balun using microstrip to CPS(Coplanar Strip) is suggested and designed. The suggested balun shows the phase imbalance of $180^{\circ}{\pm}1.5^{\circ}$ and the amplitude imbalance of ${\pm}0.2 dB$ for 1.5 to 2.5 GHz. Using the balun, DBM is successfully implemented, and the measured conversion loss of up/down converter show about 6 dB over the bandwidth. The balun may be applicable for MMIC(Monolithic Microwave Integrated Circuit) DBM with the process supporting backside via though more study.

• 전력전자학회논문지
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• 제9권1호
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• pp.36-41
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• 2004

본 논문에서는 이중접속 방식의 멀티스텝 인버터를 이용한 대용량 STATCOM에 관하여 동작원리 및 제어 방식을 기술하기로 한다. 기존의 12-스텝 인버터에 상간 변압기 및 간단한 보조회로를 이용하여 출력전압의 파형을 36-스텝으로 개선하였다. 이러한 방식의 인버터는 특히 10Mvar∼30Mvar급 전후의 STATCOM에 적용하면 경제적이다. 2KVA급 STATCOM 시작품의 실험결과로부터 제안한 방식의 타당성을 입증하였다.

• Journal of Power Electronics
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• 제19권6호
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• pp.1486-1495
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• 2019

Dealing with the DC link fault poses a technical problem for an HVDC based on a modular multilevel converter. The fault suppressing mechanisms of several sub-module topologies with DC fault current blocking capacity are examined in this paper. An improved half-bridge sub-module topology with double direction control switch is also designed to address the additional power consumption problem, and a sub-module topology called hybrid double direction blocking sub module (HDDBSM) is proposed. The DC fault suppression characteristics and sub-module capacitor voltage balance problem is also analyzed, and a self-startup method is designed according to the number of capacitors. The simulation model in PSCAD/EMTDC is built to verify the self-startup process and the DC link fault suppression features.

• 대한전자공학회논문지SD
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• 제48권10호
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• pp.72-81
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• 2011

본 논문에서는 IEEE754 표준의 단정도 및 배정도를 지원하는 새로운 부동소수점 변환기를 제안하고 설계하였다. 제안된 변환기는 부호 있는 정수(32비트/64비트)와 부동소수점(단정도/배정도) 간 변환, 부호 없는 정수(32비트/64비트)를 부동소수점(단정도/배정도)으로의 변환, 부동소수점 단정도와 배정도 간 변환뿐만 아니라 부호 있는 고정소수점(32비트 64비트)과 부동소수점(단정도 배정도) 간 변환을 지원한다. 모든 입력 형태를 하나의 형태로 만드는 새로운 내부 형태를 정의함으로써 출력 형태의 표현 범위에 따른 오버플로우 검사를 쉽게 하도록 하였다. 내부 형태는 IEEE754 2008 표준에서 정의된 부동소수점 배정도의 확장된 형태(extended format)와 유사하다. 이 표준에서는 부동소수점 배정도의 확장된 형태(extended format)의 최소 지수부 비트폭은 15비트라고 명시하지만 제안된 컨버터를 구현하는데 11비트만으로도 충분하다. 또한 덧셈기가 대신 +1 증가기를 사용하면서 라운딩 연산과 음수의 정확한 표현이 가능하도록 변환기의 라운딩 스테이지를 최적화하였다. 단일 클럭 사이클 데이터패스와 5단 파이프라인 데이터패스를 설계하였다. 변환기의 두 데이터패스에 대한 HDL 모델을 기술한 후에 Synopsys design compiler를 사용하여 TSMC 180nm 공정 라이브러리로 합성하였다. 합성 결과의 셀 면적은 12,886 게이트(2입력 NAND 게이트 기준)이고 최대 동작 주파수는 411MHz이다.

• Journal of Power Electronics
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• 제18권2호
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• pp.343-355
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• 2018

A wide-voltage-conversion range bidirectional DC-DC converter is proposed in this paper. The topology is comprised of one typical LC energy storage component and a special common grounded asymmetric H-bridge with four active power switches/anti-parallel diodes. The narrow output PWM voltage is generated from the voltage difference between two normal (wider) output PWM voltages from the asymmetric H-bridge with duty cycles close to 0.5. The equivalent switching frequency of the output PWM voltage is double the actual switching frequency, and a wide step-down/step-up ratio range is achieved. A 300W prototype has been constructed to validate the feasibility and effectiveness of the proposed bidirectional converter between the variable low voltage side (24V~48V) and the constant high voltage side (200V). The slave active power switches allow ZVS turn-on and turn-off without requiring any extra hardware. The maximum conversion efficiency is 94.7% in the step-down mode and 93.5% in the step-up mode. Therefore, the proposed bidirectional topology with a common ground is suitable for energy storage systems such as renewable power generation systems and electric vehicles with a hybrid energy source.