• The Magazine of Kiice
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• v.3 no.1
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• pp.37-40
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• 2002

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.917-921
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• 2013

This paper have analyzed the change of breakdown voltage for conduction path of double gate(DG) MOSFET. The low breakdown voltage among the short channel effects of DGMOSFET have become obstacles of device operation. The analytical solution of Poisson's equation have been used to analyze the breakdown voltage, and Gaussian function been used as carrier distribution to analyze closely for experimental results. The change of breakdown voltages for conduction path have been analyzed for device parameters such as channel length, channel thickness, gate oxide thickness and doping concentration. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. Resultly, we know the breakdown voltage is greatly influenced on the change of conduction path for device parameters of DGMOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.887-890
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• 2005

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin updoped Si channel for SCEs control, are being validated for sub-20nm scaling, A channel effects such as the subthreshold swing(SS), and the threshold voltage roll-off(${\Delta}V_{th}$). The propsed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1463-1469
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• 2012

This paper has presented the influence of scaling theory on short channel effects of double gate(DG) MOSFET in subthreshold region. In the case of conventional MOSFET, to preserve constantly output characteristics,current and switching frequency have been analyzed based on scaling theory. To analyze the results of application of scaling theory for short channel effects of DGMOSFET, the changes of threshold voltage, drain induced barrier height and subthreshold swing have been observed according to scaling factor. The analytical potential distribution of Poisson equation already verified has been used. As a result, it has been observed that threshold voltage among short channel effects is grealty changed according to scaling factor. The best scaling theory for DGMOSFET has been explained as using modified scaling theory, applying weighting factor reflected the influence of two gates when scaling theory has been applied for channel length.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1311-1316
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• 2016

This paper analyzes the influence of tunneling current on threshold voltage shift by channel length of short channel asymmetric double gate(DG) MOSFET. Tunneling current significantly increases by decrease of channel length in the region of 10 nm below, and the secondary effects such as threshold voltage shift occurs. Threshold voltage shift due to tunneling current is not negligible even in case of asymmetric DGMOSFET to develop for reduction of short channel effects. Off current consists of thermionic and tunneling current, and the ratio of tunneling current is increasing with reduction of channel length. The WKB(Wentzel-Kramers-Brillouin) approximation is used to obtain tunneling current, and potential distribution in channel is hermeneutically derived. As a result, threshold voltage shift due to tunneling current is greatly occurred for decreasing of channel length in short channel asymmetric DGMOSFET. Threshold voltage is changing according to bottom gate voltages, but threshold voltage shifts is nearly constant.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.768-771
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• 2013

This paper analyzed the change of subthreshold current for channel doping concentration of double gate(DG) MOSFET. Poisson's equation had been used to analyze the potential distribution in channel, and Gaussian function had been used as carrier distribution. The potential distribution was obtained as the analytical function of channel dimension, using the boundary condition. The subthreshold current had been analyzed for channel doping concentration, and projected range and standard projected deviation of Gaussian function. Since this analytical potential model was verified in the previous papers, we used this model to analyze the subthreshold current. As a result, we know the subthreshold current was influenced on parameters of Gaussian function and channel doping concentration for DGMOSFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1617-1622
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• 2015

This paper analyzes the ratio of tunneling current for channel doping concentration of sub-10 nm asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current in subthreshold region increases in the region of channel length of 10 nm below. Even though asymmetric DGMOSFET is developed to reduce short channel effects, the increase of tunneling current in sub-10 nm is inevitable. As the ratio of tunneling current in off current according to channel doping concentration is calculated in this study, the influence of tunneling current to occur in short channel is investigated. To obtain off current to consist of thermionic emission and tunneling current, the analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for channel doping concentration in sub-10 nm asymmetric DGMOSFET, specially with parameters of channel length, channel thickness, and top/bottom gate oxide thickness and voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1196-1202
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• 2013

This paper have analyzed the change of breakdown voltage for channel doping concentration and device parameters of double gate(DG) MOSFET using two dimensional potential model. The low breakdown voltage becomes the obstacle of power device operation, and breakdown voltage decreases seriously by the short channel effects derived from scaled down device in the case of DGMOSFET. The two dimensional analytical potential distribution derived from Poisson's equation have been used to analyze the breakdown voltage for device parameters such as channel length, channel thickness, gate oxide thickness and channel doping concentration. Resultly, we could observe the breakdown voltage has greatly influenced on device dimensional parameters as well as channel doping concentration, especially the shape of Gaussian function used as channel doping concentration.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.457-458
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• 2014

In this paper, quantum mechanical simulations of the double-gate ultra-thin body (DG-UTB) MOSFETs are performed according to the International Technology Roadmap of Semiconductors (ITRS) specifications planned for 2020, to devise the way for on-current ($I_{on}$) improvement. We have employed non-equilibrium Green's function (NEGF) approach and solved the self-consistent equations based on the parabolic effective mass theory [1]. Our study shows that the [100]/<001> Ge and GaSb channel devices have higher $I_{on}$ than Si channel devices under the body thickness ($T_{bd}$) <5nm condition.