• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.314-316
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• 1997

We have studied the epitaxial growth and electrical properties of $Si_{0.8}Ge_{0.2}$, films on Si substrates at $550^{\circ}C$ by LPCVD. In a low $PH_3$, partial pressure region such as below 1.25 mPa, the phosphorus doping concentration increased proportionally with increasing $PH_3$ partial pressure while the deposition rate and the Ge fraction x were constant. In a higher $PH_3$ partial pressure region, the phosphorus doping concentration and the deposition rate decreased, while the Ge fraction slightly increased. The dependence of P incorporation rate on the $PH_3$ partial pressure was similar to the phosphorus doping concentration. According to test results, it suggests that high surface coverage of phosphorus atoms suppress both the $SiH_4$ adsorption/reaction and the $GeH_4$ adsorption/reaction on the surfaces, and the effect is more stronger on $SiH_4$ than on $GeH_4$. In a higher $PH_3$ partial pressure region, the deposition is largely controlled by surface coverage effect of phosphorus atoms.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.421-422
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• 2013

Recently, ZnO has received attentionbecause of its applications in optoelectronics and spintronics. In order to investigate deep level defects in ZnO, we used N-doped ZnO with various of the N-doping concentration. which are reference samples (undoped ZnO), 27%, 49%, and 88%-doped ZnO. Photoinduced current transient spectroscopy (PICTS) measurement was carried out to find deep level traps in high resistive ZnO:N. In reference ZnO sample, a deep trap was found to located at 0.31 (as denoted as the CO trap) eV below conduction band edge. And the CN1 and CN2 traps were located at 0.09, at 0.17 eV below conduction band edge, respectively. In the case of both annealed samples at 200 and $300^{\circ}C$, the defect density of the CO trap increases and then decreases with an increase of N-doping concentration. On the other hands, the density of CN traps has little change according to an increase of N-doping concentration in the annealed sample at $300^{\circ}C$. According to the result of PICTS measurement for different N-doping concentration, we suggest that the CO trap could be controled by N-doping and the CN traps be stabilized by thermal annealing at $300^{\circ}C$.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 추계학술대회 초록집
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• pp.63.2-63.2
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• 2011

결정질 실리콘 웨이퍼를 이용한 고효율 태양전지를 제작하기 위해서는 반드시 고려해야 할 주요 인자들이 있다. 그 중에서도 Base resistivity, Thickness, Doping concentration, Texture size, Texture angle등의 주요 인자를 PC1D 시뮬레이션 프로그램을 이용하여 최적화 해 보았다. 그 결과, Base resistivity값은 낮을수록 좋으나 지나치게 낮을 경우 재결합으로 인해 효율이 떨어지기 때문에 Base resistivity = $1{\Omega}{\cdot}cm$에서 최대 효율을 얻을 수 있었다. 또한, Thickness는 두꺼울수록 R=${\rho}$(L/A)의 식에 의해 직렬저항이 증가하여 효율이 감소하므로 Thickness = $200{\mu}m$ 정도가 적정 값임을 확인할 수 있었다. Doping concentration의 경우 높을수록 재결합으로 인해 효율이 떨어지며 Doping concentration = $3.69{\times}10^{-20}cm^{-3}$에서 가장 좋은 효율을 보였다. Textrure size와 Textrure angle은 그 값이 클수록 빛의 흡수 정도가 증가해 효율이 증가함을 볼 수 있었고 Textrure size = $2{\sim}4{\mu}m$, Texture angle = $79^{\circ}$에서 높은 효율을 보여주었다. 이와 같은 조건에서 고효율 태양전지를 제작을 위한 시뮬레이션을 한 결과, 16.23%의 변환효율을 얻을 수 있었다.

• 한국정보통신학회논문지
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• 제19권7호
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• pp.1617-1622
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• 2015

본 연구에서는 10 nm이하 채널길이를 갖는 비대칭 이중게이트 MOSFET의 채널도핑농도 변화에 대한 터널링 전류(tunneling current)의 변화에 대하여 분석하고자 한다. 채널길이가 10 nm이하로 감소하면 차단전류에서 터널링 전류의 비율이 문턱전압이하 영역에서 차지하는 비율이 증가하게 된다. 비록 비대칭 이중게이트 MOSFET가 단채널효과를 감소시키기 위하여 개발되었을지라도 10 nm 이하에서 터널링 전류에 의한 차단전류의 증가는 필연적이다. 본 연구에서는 채널도핑농도의 변화에 대하여 차단전류 중에 터널링 전류의 비율 변화를 계산함으로써 단채널에서 발생하는 터널링 전류의 영향을 관찰하고자 한다. 열방사 전류와 터널링 전류로 구성된 차단전류를 구하기 위하여 포아송방정식을 이용하여 해석학적 전위분포를 구하였으며 WKB(Wentzel- Kramers-Brillouin) 근사를 이용하여 터널링 전류를 구하였다. 결과적으로 10 nm이하의 채널길이를 갖는 비대칭 이중게이트 MOSFET에서는 채널도핑농도에 의하여 터널링 전류가 크게 변화하는 것을 알 수 있었다. 특히 채널길이, 채널두께, 상하단 게이트 산화막 및 전압 등의 파라미터에 따라 매우 큰 변화를 보이고 있었다.

• Elastomers and Composites
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• 제56권4호
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• pp.250-253
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• 2021

Polypyrrole is an organic thermoelectric material which has been receiving extensive attention in recent years. Polypyrrole is applicable in various fields because its electrical properties are controllable by its doping concentration. In this study, the effects of the polypyrrole doping state on its photoresponse were investigated. The degree of doping was controlled by ammonia solution treatment. Then, the chemical structure as a function of the doping states was observed by Raman analysis. Moreover, the photocurrent and photovoltage characteristics for various doping states were measured by an asymmetrically irradiated light source. As the degree of doping increased, the electrical conductivity increased, which affected the photocurrent. Meanwhile, the photovoltage was related to the temperature gradient caused by light irradiation.

• 한국세라믹학회지
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• 제37권2호
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• pp.194-200
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• 2000

Sb-doped tin oxide films were deposited on Corning glass 1737 substrate by plasma enhanced chemical vapor deposition(PECVD) technique using a gas mixture of SnCl4/SbCl5/O2/Ar. The deposition behaviors of tin oxide films by PECVD were compared with those by thermal CVD, and effects of deposition temperature, r.f. power and Sb doping on the electrical properties of tin oxide films were investigated. PECVD technique largely increased the deposition rate and smoothed the surface of tin oxide films compared with thermal CVD. Electrical resistivity decreased with doping of Sb due to the increase of carrier concentration. However, large doping of Sb diminished carrier concentration and mobility due to the decrease of crystallinity, which resulted in the increase of electrical resistivity. As the deposition temperature and r.f. power increased, Cl content in the film decreased.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.210-215
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• 1994

In the CMOS device, Counter doping is needed to adjust threshold voltage because of the difference between n-MOSFET and p-MOSFET well doping concentration when n+ polysilicon gate is used. Therefore buried channel is formed in the p-channel MOSFET degrading properties. So well doping concentration and doping condition should be considered in fabrication process and device design. Here we are to extract the initial process condition using simulation and fabricate p-MOSFET device and then compare the subthreshold characteristics of simulated and fabricated device.

• 대한전기학회논문지
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• 제38권6호
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• pp.401-415
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• 1989

A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권5호
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• pp.299-301
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• 2000

Analytical expression for the breakdown voltage of the gated diodes were derived as f function of doping concentration and gate voltage, and verified by numerical simulations using ATLAS. The analytical results are in good agreement with simulation results within 5% error when the gate voltage changes from -50V to 130V in case of ND = $1\times1015 cm^{-3}$ and within 10% error when the doping concentration is changed from $5\times1014 cm^{-3}\; to\; 2\times1015 cm6{-3}$, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.256-256
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• 2009

This paper presents a proper condition to achieve above 17 % conversion efficiency using PC1D simulator. Crystalline silicon wafer with thickness of $240{\mu}m$ was used as a starting material. Various efficiency influencing parameters such as rear surface recombination velocity and minority carrier diffusion length in the base region, front surface recombination velocity, junction depth and doping concentration in the Emitter layer. Among the investigated variables, we learn that 2nd doping concentration as a key factor to achieve conversion efficiency higher than 17 %.