• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.79-85
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• 2005

In this paper, low-power design and implementation techniques for IMT-2000 interpolation filter are proposed. Processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized for low-power implementation. proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of filter coefficient. Finally, in third shift register block, multiplied values are output and stored in shift register. For IMT-2000 interpolation filter, proposed and conventional structures are implemented by using Verilog-HDL coding. Gate counts for the proposed structure is reduced to 31.57% comparison with those of the conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2A
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• pp.116-123
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• 2002

The jacket matrix is based on the Walsh-Hadamard matrix and an extension of it. While elements of the Walsh-Hadamard matrix are +1, or -1, those of the Jacket matrix are ${\pm}$1 and ${\pm}$$\omega$, which is $\omega$, which is ${\pm}$j and ${\pm}$2$\sub$n/. This matrix has weights in the center part of the matrix and its size is 1/4 of Hadamard matrix, and it has also two parts, sigh and weight. In this paper, instead of the conventional Jacket matrix where the weight is imposed by force, a simple Jacket sequence generation method is proposed. The Jacket sequence is generated by AND and Exclusive-OR operations between the binary indices bits of row and those of column. The weight is imposed on the element by when the product of each Exclusive-OR operations of significant upper two binary index bits of a row and column is 1. Each part of the Jacket matrix can be represented by jacket sequence using row and column binary index bits. Using Distributed Arithmetic (DA), we present a VLSI architecture of the Fast Jacket transform is presented. The Jacket matrix is able to be applied to cryptography, the information theory and complex spreading jacket QPSK modulation for WCDMA.

• Journal of Korea Game Society
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• v.13 no.2
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• pp.39-48
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• 2013

In MMORPGs(Massively Multi-player Online Role-Playing Games) a large number of players actively interact with one another in a virtual world. Therefore MMORGs must be able to quickly process real-time access requests and process requests from numerous gaming users. A key challenge is that the workload of the game server increases as the number of gaming users increases. To address this workload problem, many developers apply with distributed server architectures which use dynamic map partitioning and load balancing according to the server function. Therefore most MMORPG servers partition a virtual world into zones and each zone runs on multiple game servers. These methods cause of players frequently move between game servers, which imposes high overhead for data updates. In this paper, we propose a new architecture that apply with an arithmetic server dedicated to data operation. This architecture enables the existing game servers to process more access and job requests by reducing the load. Through mathematical modeling and experimental results, we show that our scheme yields higher efficiency than the existing ones.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.8 no.2
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• pp.123-133
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• 2010

A statistical evaluation methodology was developed to determine the compliance of candidate waste stream with clearance criteria based upon distribution of radionuclide in a waste stream at a certain confidence level. For the cases where any information on the radionuclide distribution is not available, the relation between arithmetic mean of radioactivity concentration and its acceptable maximum standard deviation was demonstrated by applying widely-known Markov Inequality and One-side Chebyshev Inequality. The relations between arithmetic mean and its acceptable maximum standard deviation were newly derived for normally or lognormally distributed radionuclide in a waste stream, using probability density function, cumulative density function, and other statistical relations. The evaluation methodology was tested for a representative case at 95% of confidence level and 100 Bq/g of clearance level of radioactivity concentration, and then the acceptable range of standard deviation at a given arithmetic mean was quantitatively shown and compared, by varying the type of radionuclide distribution. Furthermore, it was statistically demonstrated that the allowable range of clearance can be expanded, even at the same confidence level, if information on the radionuclide distribution is available.

• Journal of the Korean Home Economics Association
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• v.24 no.2
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• pp.93-112
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• 1986

The purpose of this study is to clarify which some factors among the socio-demographic factors have effect on the housewives behavior on how to buy small electric appliances and how to use them. The questionnaires were distributed in July 1985 to 491 housewives in Seoul. Satistical methods as percentage, frequency, arithmetic mean, chi-square test, t-test and F-test were used for data analysis. RESULTS : 1) The average rate of possessing the automatic rice cooker is 87.8%, the electric frypan is 81.0%, the toaster is 36.9% and the blender is 86.9%. 2. Generally the frequency of use were low. 3) Generally their knowledge on small electric appliances is low. 4) The ability of management in blender was influenced by age, education and in automatic rice cooker was influenced by only education.

• Journal of Environmental Science International
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• v.29 no.1
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• pp.25-32
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• 2020

The determination of soil parameters is important in predicting the simulated surface runoff using either a distributed or a lumped rainfall-runoff model. Soil characteristics can be collected using remote sensing techniques and represented as a digital map. There is no universal agreement with respect to the determination of a representative parameter from a gridded digital map. Two representative methods, i.e., arithmetic and predominant, are introduced and applied to both FLO-2D and HEC-HMS to improve the model's accuracy. Both methods are implemented in the Yongdam catchment, and the results show that the former seems to be more accurate than the latter in the test site. This is attributed to the high conductivity of the dominant soil class, which is A type.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8C
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• pp.812-818
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• 2002

반도체 기술과 멀티기디어 통신기술이 발달하면서 고품위의 영상과 다중 채널의 오디오에 관심을 갖게되었다. 특히 DVD 시장의 급성장으로 인하여 고품질의 영상 및 오디오 필요성이 중요한 기술로 대두되었다. MPEG-Audio 표준안은 어떠한 비트율도 지원한다. 본 논문에서는 MPEG-Audio의 핵심부분인 필터부분을 DALUT (Distributed Arithmetic Look-Up Table)방식을 사용하여 FPGA(Field Programmable Gate Array)에 구현하였다. 고속 필터를 설계하기 위해서 승산기 대신에 DALUT를 사용하였으며 최소 10㎒에서 최대 30㎒ 사이에서 동작한다. 본 논문의 설계는 모두 VHDL로 구현하였으며, 알고리즘 검증은 C언어를 사용하였다. VHDL의 시뮬레이션은 ALDEC사의 Active-HDL5.1과 Synopsys사의 vhdlsim을 사용하였고, 합성은 Synopsys사의 design-analyzer를 사용하였다. 타겟 라이브러리는 XILINX사의 XC4010E, XC4020EX, XC4052XL을 사용하였으며, P＆R 툴은 XACT Ml.4를 사용하였다.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.653-662
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• 1989

Cerebellar Model Arithmetic Controller (CMAC) has been introduced as an adaptive control function generator. CMAC computes control functions referring to a distributed memory table storing functional values rather than by solving equations analytically or numerically. CMAC has a unique mapping structure as a coarse coding and supervisory delta-rule learning property. In this paper, learning aspects and a convergence of the CMAC were investigated. The efficient training algorithms were developed to overcome the limitations caused by the conventional maximum error correction training and to eliminate the accumulated learning error caused by a sequential node training. A nonlinear function generator and a motion generator for a two d.o.f. manipulator were simulated. The efficiency of the various learning algorithms was demonstrated through the cpu time used and the convergence of the rms and maximum errors accumulated during a learning process. A generalization property and a learning effect due to the various gains were simulated. A uniform quantizing method was applied to cope with various ranges of input variables efficiently.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.702-708
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• 2000

In this paper, we designed one-dimensional VLSI array with optimal pipeline period for high speed processing fractal image compression. The algorithm is derived which is suitable for VLSI array from axed block partition algorithm. Also the algorithm satisfies high quality of image and high compression-ratio. The designed VLSI array has optimal pipeline relied because the required processing time of PEs is distributed as same as possible. As this result, we can improve the processing speed up to about 3 times. The number of input/output pins can be reduced by sharing the input/output and arithmetic unit of the domain blocks and the range blocks.