• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.7-10
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• 2007

최근 이동통신을 이용해 다양한 서비스를 제공하기 위하여 멀티 밴드, 멀티 채널의 송수신기를 단일칩화 하기 위한 연구가 활발히 진행되고 있다. CMOS 집적 회로 기술은 가격 경쟁력이 높고 집적도가 높아 멀티 밴드, 멀티 채널 송수신기를 집적화하기에 적합하다. 그러나 0.18 ${\mu}m$ 이하의 채널 길이를 갖는 CMOS 집적 회로는 1.8 V 이하의 낮은 공급 전압을 제공함으로 높은 이득을 갖는 mixer의 구현이 어렵고, mixer에서 발생되는 2, 3차 상호 변조에 의한 왜곡으로 선형성이 문제가 된다. 이런 문제점을 해결하기 위해서 기능성 능동부하를 적용하여 선형성을 향상한 Direct Conversion Down Mixer를 설계 분석 하였다.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.114-118
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• 2008

Direct-conversion RF front-end for 5-GHz WLAN is implemented in $0.18-{\mu}m$ CMOS technology. The front-end consists of a low noise amplifier, and low flicker noise down-conversion mixers. For the mixer, an inductor is included to resonate out parasitic tail capacitances in the transconductance stage at the operating frequency, thereby improves the flicker noise performance of the mixer, and the overall noise performance of the front-end. The receiver RF front-end has 6.5 dB noise figure, - 13 dBm input IP3, and voltage conversion gain of 20 dB with the power consumption of 30 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.45-49
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• 2009

In this paper, a direct down conversion LNA/Mixer has been designed and tested for 900Mhz UHF RFID application. The designed circuit has been implemented in 0.18um CMOS technology with 3.3V operation. In this work, a common gate input architecture has been used to cope with the higher input self jamming level. This LNA/Mixer is designed to support two operating modes of high gain mode and low gain mode according to the input jamming levels. The measured results show that the input referred P1dBs are 4dBm of high gain mode and 11dBm of low gain mode, and the conversion gains are 12dB and 3dB in high and low gain mode respectively The power consumptions are 60mW for high gain mode and 79mW for low gain mode. The noise figures are 16dB and 20dB in high gain mode and low gain mode respectively.

• Journal of Electrical Engineering and Technology
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• v.7 no.1
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• pp.81-85
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• 2012

This paper presents a wideband and low-noise direct conversion front-end receiver supporting VHF and UHFbands simultaneously. The receiver iscomposed of a low-noise amplifier (LNA), a down conversion quadrature mixer, and a frequency divider by 2. The cascode configuration with the resistor feedback is exploited in the LNA to achieve a wide operating bandwidth. Four gainstep modesare employed using a switched resistor bank and a capacitor bank in the signal path to cope with wide dynamic input power range. The verticalbipolar junction transistors are used as the switching elements in the mixer to reduce 1/f noise corner frequency. The proposed front-end receiver fabricated in 0.18 ${\mu}m$ CMOS technology shows very low minimum noise figureof 1.8 dB and third order input intercept pointof -12dBm inthe high-gain mode of 26.5 dBmeasured at 500 MHz.The proposed receiverconsumeslow current of 20 mA from a 1.8 V power supply.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.7-15
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• 2002

The digital DBS tuner is designed and implemented in a CMOS process using a direct-conversion architecture that offers a high degree of integration. To generate mathched LO I/Q quadrature signals covering the total input frequency range, a fully integrated ring oscillator is employed. And, to decrease a high level of phase noise of the ring oscillator, a frequency synthesizer is designed using a double loop strucure. This paper proposes and verifies a band selective loop for fast frequency switching time of the double loop frequency synthesizer. The down-conversion mixer with source follower input stages is used for low voltage operation. An experiment implementation of the frequency synthesizer and mixer with integrated a 0.25um CMOS process achieves a switching time of 600us when frequency changes from 950 to 2150MHz. And, the experiment results show a quadrature amplitude mismatch of max. 0.06dB and a quadrature phase mismathc of max. >$3.4^{\circ}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.189-193
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• 2005

In this paper, we propose a direct conversion double-balanced down-converter fer MB-OFDM W system, which is implemented using $0.18\;{\mu}m$ CMOS technology and its measurement results are shown. The proposed down-converter adopts a resistive current-source instead of general transconductance stage using MOS transistor to achieve wideband characteristics over RF input frequency band $3\~5\;GHz$ with good gain flatness. The measured conversion gain is more than +3 dB, and gain flatness is less than 3 dB for three UWB channels. The dc consumption of this work is only 0.89 mA from 1.8 V power supply, leading to the low-power W application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.51-57
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• 2010

A dual-mode direct conversion receiver is developed in $0.13\;{\mu}m$ RF CMOS process for IEEE 802.11n based wireless LAN and IEEE 802.16e based mobile WiMAX application. The RF receiver covers the frequency band between 2.3 and 2.7 GHz. Three-step gain control is realized in LNA by using current steering technique. Current bleeding technique is applied to the down-conversion mixer in order to lower the flicker noise. A frequency divide-by-2 circuit is included in the receiver for LO I/Q differential signal generation. The receiver consumes 56 mA at 1.4 V supply voltage including all LO buffers. Measured results show a power gain of 32 dB, a noise figure of 4.8 dB, a output $P_{1dB}$ of +6 dBm over the entire band.