• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.668-675
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• 2001

Recently, the performance of the commercial PCS(Personal Communication Service) system has been improved to the uppermost limit and ultimately the next generation mobile communication is to be realized by IMT-2000 (International Mobile Communication-2000) to provide multimedia services. Therefore, the new type receiving system is researched actively and one of the most important part in a receiver is direct conversion method. The direct conversion method is suitable for low power consumption, small size, MMIC, and low price, which is to be adopted to the next generation mobile communication systems. In this case, however, several problems occur due to DC-offset. The DC-offset suppresses amplification of the required signal because of the leakage signal of frequency synthesizer in the system. In this thesis, the removing method of DC-offset was considered. There are four removing techniques of DC-offset, which are AC-coupling, large capacitor, DC-feedback loop, and DC-free coding. Among these, the AC-coupling method is the most simplest method and the DC-feedback loop method has the best performance. Then, the performance of the AC-coupling method and DC-feedback loop method are evaluated by HP's ADS simulation tool. As a result, the AC-coupling method cannot be used to the digital communication systems due to data loss. On the other hand, it was confirmed that the DC-feedback loop method is suitable for the direct conversion receiver.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2008.04a
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• pp.613-617
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• 2008

One of the important parts on multimedia era is acoustic ones. With increased demand of smallest multimedia products such as personal digital assistant (PDA) and mobile phones, it is necessary to develop acoustic devices which have higher performance and smaller size. Acoustic parts with various function for hearing impaired persons. This paper introduces a bone conduction vibrator (BCV) for hearing impaired persons to use portable acoustic device without additional devices. For vibration analysis of the BCV, electromagnetic, mechanical and their coupling effects are considered for the analysis. This paper shows that the development of design and analysis technique by finite element method (FEM) of BCV.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.211-216
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1130-1137
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• 2009

This paper proposes a new clock routing design for suppressing clock harmonic effects in a Printed Circuit Board (PCB) for a terrestrial Digital Multimedia Broadcasting(DMB) system. Typical crystal reference frequencies that are widely used in DMB tuners are 16.384 MHz, 19.2 MHz, 24.576 MHz. When the high-order harmonic components of these reference frequencies fall near the RF channel frequencies, receiver sensitivity of the tuners is seriously degraded. In this work, we propose a new clock routing design in order to address the clock harmonic coupling issue. The proposed design incorporates two inductors for isolating the clock ground from the main ground, and adopts a new strip line-style routing instead of the conventional microstrip line style routing to minimize the overlap area with the main ground. As a result, the RF sensitivity of the T-DMB tuner is improved by 2 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.61-70
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• 2009

A 10b 30MS/s pipelined ADC operating under 1V power supply is presented. It utilizes a switched-RC based input sampling circuit and a resistive loop to reset the feedback capacitor in the multiplying digital-to-analog converter (MDAC) for the low-voltage operation. Cascaded switched-RC branches are used to achieve accurate grain of the MDAC for the first stage and separate switched-RC circuits are used in the sub-ADC to suppress the switching noise coupling to the MDAC input The measured differential and integral non-linearities of the prototype ADC fabricated in a 0.13${\mu}m$, CMOS process are less than 0.54LSB and 1.75LSB, respectively. The prototype ADC achieves 54.1dB SNDR and 70.4dB SFDR with 1V supply and 30MHz sampling frequency while consuming 17mW power.