• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.429-430
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• 2008

본 논문은 전기출력이 1400 MWe급으로 개발된 첨단 원자력 발전소인 APR1400(신형겨수로 1400) 제어계통에 적용되는 디지털시스템의 설계 및 성능 검증을 위해 개발 중인 디지털제어계통 검증시스템에 관한 것이다. APR1400 디지털제어계통은 발전소 출력 제어 및 안전운전과 관련 된 중요 기능들을 수행하며, 기존 원자력발전소와 달리 단일 디지털 Platform을 적용하고, Multi-Loop 개념과 네트워크을 적용하여 Controller와 케이블 수량을 줄인 특징을 가지고 있다. 이와 같을 설계는 지금가지 원자력발전소에는 적용된 적이 없기 때문에 사용자 측면에서는 디지털 제어 계통 설계 및 성능 관점에서의 검증을 위한 시스템이 요구되었다. 현재는 APR1400 시뮬레이터(발전소 모델링을 통한 모의시스템)를 이용한 검증시스템을 1차적으로 구축한 상태에 있으며, 시스템 전체 시험을 진행 중에 있다. 특히, 이번에 개발 중인 검증시스템은 구성이 간단하고 사용이 편리한 장점을 지니고 있을 뿐만 아니라 다양한 고장상황을 재현해 봄으로써 디지털제어계통의 성능을 확인해 볼 수 있는 특징을 보유하고 있다. 본 검증시스템의 활용방안으로는 첫째, 계통설계의 구현 가능성 관점에서의 확인시험을 수행하는 방안, 둘째, 발전소 시운전 착수 전 시운전요원 교육에 활용하는 방안, 셋째, 발전소 설계 변경 필요 시 설계 변경에 따른 영향 파악, 넷째, 디지털제어계통 유지보수 기술 습득 등에 효과적으로 활용 할 수 있을 것으로 본다. AFR1400 디지털제어계통은 현재 건설 중인 신고리 3,4호기 원자력발전소에 적용될 예정이며, 향후에는 해외 원자력 수출을 위한 기반기술로 활용될 수 있을 것으로 확신한다.

• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.31-42
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• 2005

ATSC DTV system uses FPLL block for acquiring the frequency synchronization. Because the FPLL uses only the pilot signal, the frequency convergence range becomes narrower and it takes a more time to acquire the frequency synchronization as the pilot is distorted. And the spectrum shape around the pilot makes an asymmetric convergence range between the positive frequency offset and the negative frequency offset. This paper proposes the algorithm that requires the Installation of the fitters at the both edges of a VSB spectrum and uses the signal power that passes these filters. The proposed algorithm complements the problems of the asymmetric convergence range and overcomes the performance degradation due to the distortion of a pilot level.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.429-440
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• 2007

A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1120-1128
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• 2004

In this paper, we has designed and implemented Up-converter for K-band with high IMD3 performance using balanced power amplifier. It is consisted of PA module and, Local Oscillator module with reject Filter, mixer module and If block, and Up-converter has a local loop path to decide whether it operate or not and has the sensing port to inspect output power level. According to the power budget of designed Up-converter, K-band balanced power amplifier was fabricated by commercial MMIC. Measurement results of up-converter show about 40dB Gain, PldB of 29dBm and OIP3 was 38.25dBm, that is good performance compared to power budgets. We has adjusted gate voltage of MMIC to control more than 30 dB gain. This up-converter was used in transceiver for PTP and PTMP, and applied to digital communication system that use QAM and QPSK modulation.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.127-134
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• 2009

In spite of controversial debates on aesthetic issues of computer-generated electronic music, rapid advancement of music technologies in the past decade have resulted proliferation of using virtual software synthesizers and samplers in music composition. Computer-based music production platform has become not only a norm among some of contemporary music composers but also vital apparatus for their compositional process. There are two imperative parts of this compositional process involving sampling in computer-based music production, which are commercially available sample libraries that include pre-recorded audio samples, and music production software that processes them. The purpose of this study is to investigate the process and effectiveness of reconstructive compositional process utilizing distinctive features of sampling on computer music production software. This study addresses issues such as: the definition of audio sampling, how sampling is incorporated in compositional process, and what features of music production software are particularly effective in various musical expressions. The result of this study will hopefully accommodate and fulfill the needs of electronic and acoustic musicians' creativeness.

• The Transactions of the Korea Information Processing Society
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• v.4 no.5
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• pp.1371-1379
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• 1997

Undetectable faults in a digital circuit are faults that no input patterms can detect.Identifying these faults in test geferation process is very time- consuming especially for sequential circuits .In this paper we present a new algorithm to identify unedtectable faults in sequential cirouits .In the alorithm. we identify uninitializable fip-flops and then, faults that prevent intialization of the fkip-flops(FPIs)are identified, finally propagation path of the FPI is checked. Time complexity of this algorithm is porportional to the product of the number of flip flops with at lest a self loop and the number of gates in the circuit. Experiments were performed on the ISCAS89 benchmark ciruits to show the feadibility of the proposed algorithm.We could identify large amount of undetectable faults(up to 50% of the number of flip-flops)in circuits with uninitializable flip-flops. Consider-ing that most of the time in test generation is cinsumed in identifying undetecatable faults, performance of test generator can be improved by using this algorithm as a pre-processing of test generation.

• Journal of Power Electronics
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• v.18 no.2
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• pp.558-572
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• 2018

In addition to its modular nature, a Hybrid Modular Multilevel Converter (HMMC) assembled from half-bridge and full-bridge sub-modules, is able to block DC faults with a minimum number of switching devices, which makes it attractive for high power applications. This paper introduces a control strategy based on the Root-Least Square (RLS) algorithm to estimate the capacitor voltages instead of using direct measurements. This action eliminates the need for voltage transducers in the HMMC sub-modules and the associated communication link with the central controller. In addition to capacitor voltage balancing and suppression of circulating currents, a fault tolerant control unit (FTCU) is integrated into the proposed strategy to modify the parameters of the HMMC controller. On advantage of the proposed FTCU is that it does not need extra components. Furthermore, a fault detection unit is adapted by utilizing a hybrid estimation scheme to detect sub-module faults. The behavior of the suggested technique is assessed using PSCAD offline simulations. In addition, it is validated using a real-time digital simulator connected to a real time controller under various normal and fault conditions. The proposed strategy shows robust performance in terms of accuracy and time response since it succeeds in stabilizing the HMMC under faults.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.94-99
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• 2010

This paper presents a design procedure of digitally controlled oscillator(DCO) for power optimization. By controlling coarse tuning bits and fine tuning bits of DCO, the proposed design procedure can optimize the power dissipation and does not affect the LSB resolution, frequency range, linearity, portability. For optimization, the relationship between control bits and power dissipation of the DCO was analyzed. The DCO circuits using and unusing proposed design technique have been designed, simulated and proved using 0.13um, 1.2V CMOS library. The DCO circuit with proposed design technique has operation range between 283MHz and 1.1GHz and has 1.7ps LSB resolution and consumes 2.789mW at frequency of 1GHz.