• Journal of Power Electronics
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• v.15 no.2
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• pp.346-355
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• 2015

On the basis of the conventional PID control algorithm, a modified adaptive PID (MA-PID) control algorithm is presented to improve the steady-state and dynamic performance of closed-loop systems. The proposed method has a straightforward structure without excessively increasing the complexity and cost. It can adaptively adjust the values of the control parameters ($K_p$, $K_i$ and $K_d$) by following a new control law. Simulation results show that the line transient response of the MA-PID is better than that of the adaptive digital PID because the differential coefficient $K_d$ is introduced to changes. In addition, experimental results based on a FPGA indicate that the MA-PID control algorithm reduces the recovery time by 62.5% in response to a 1V line transient, 50% in response to a 500mA load transient, and 23.6% in response to a steady-state deviation, when compared with the conventional PID control algorithm.

• Journal of Power Electronics
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• v.10 no.4
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• pp.412-418
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• 2010

This paper proposes a new algorithm to generate a reference signal for an active power filter using a sliding-window FFT operation to improve the steady-state performance of the active power filter. In the proposed algorithm the sliding-window FFT operation is applied to the load current to generate the reference value for the compensating current. The magnitude and phase-angle for each order of harmonics are respectively averaged for 14 periods. Furthermore, the phase-angle delay for each order of harmonics passing through the controller is corrected in advance to improve the compensation performance. The steady-state and transient performance of the proposed algorithm was verified through computer simulations and experimental work with a hardware prototype. A single-phase active power filter with the proposed algorithm can offer a reduction in THD from 75% to 4% when it is applied to a non-linear load composed of a diode bridge and a RC circuit. The active power filter with the proposed reference generation method shows accurate harmonic compensation performance compared with previously developed methods, in which the THD of source current is higher than 5%.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1684-1686
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• 2005

As photovoltaic(PV) power generation systems become more common, it will be necessary to investigate islanding detection method for PV systems. Islanding of PV systems can cause a variety of problems and must be prevented. However, if the real and reactive power of load and PV system are closely matched, islanding detection by passive methods becomes difficult. Also, most active methods lose effectiveness when there are several PV systems feeding the same island. The active frequency drift positive feedback method(AFDPF) enables islanding detection by forcing the frequency of the voltage in the island to drift up or down. In this paper the research for the minimum value of chopping fraction gain applied digital phase-locked-loop(DPLL) to AFDPF considering output power quality and islanding prevention performance are performed by simulation and experiment in IEEE Std 929-2000 islanding test.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1830-1843
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• 2018

In this paper, the generation of a reference current and voltage signal based on a Kalman filter is offered for a 3-phase 4wire UPQC (Unified Power Quality Conditioner). The performance of the UPQC is improved with source voltages that are distorted due to harmonic components. Despite harmonic and frequency variations, the Kalman filter is capable enough to determine the amplitude and the phase angle of load currents and source voltages. The calculation of the first state is sufficient to identify the fundamental components of the current, voltage and angle. Therefore, the Kalman state estimator is fast and simple. A Kalman based control strategy is proposed and implemented for a UPQC in a distribution system. The performance of the proposed control strategy is assessed for all possible source conditions with varying nonlinear and linear loads. The functioning of the proposed control algorithm with a UPQC is scrutinized and validated through simulations employing MATLAB/Simulink software. Using a FPGA SPATRAN 3A DSP board, the proposed algorithm is developed and implemented. A small-scale laboratory prototype is built to verify the simulation results. The stated control scheme for the UPQC reduces the following issues, voltage sags, voltage swells, harmonic distortions (voltage and current), unbalanced supply voltage and unbalanced power factor under dynamic and steady-state operating conditions.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.75-81
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• 2021

This study analyzes the resonance characteristics caused by the mutual interference between LCL filters and the grid impedance under the parallel operation of the grid-connected inverter using the LCL filter. These characteristics are verified through simulation and experiment. Two inverters are used to connect to the grid in parallel, and the system parameters, including the LCL filter, are set to the same conditions. In the case of inverters running in parallel at the point of common coupling, the presence of grid impedance causes mutual interference between the LCL filters of each inverter, and the deviation of the filter resonance frequency is analyzed to understand the parallel inverter. The correlation between the number of devices and the size of grid impedance is simulated by PSIM and verified by MATLAB. By connecting the real-time digital simulator Typhoon HILS to the DSP 28377 control board, the mutual interference characteristics are tested under the condition of two inverters running in parallel. The experimental and analysis results are the same, indicating the validity of the analysis.

• Journal of IKEEE
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• v.23 no.2
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• pp.461-468
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• 2019

A continuous-time Delta-Sigma ADC has various benefits; it does not require an explicit anti-aliasing filter, and it is able to handle wider-band signals with less power consumption in comparison with a discrete-time Delta-Sigma ADC. However, it inherently needs to sample the signal with a high-speed clock, necessitating a complex decimation filter that operates at high speed in order to convert the modulator output to a low-rate high-resolution digital signals without causing aliasing. This paper proposes a continuous-time Delta-Sigma ADC architecture that employs pulse-width modulation and shows that the proposed architecture lends itself to a simpler implementation of the decimation filter using a lookup table.

• Journal of Drive and Control
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• v.15 no.4
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• pp.30-38
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• 2018

Electronic control units (ECUs) are currently popular, and have evolved further towards the high-end application of autonomous vehicles in the automotive industry. Such digital technologies have also become widespread, in agriculture and construction equipment. Likewise, transmission control of high-speed tracked vehicles is based on the transmission control unit (TCU), performing complex gear change control functions, and diagnostic algorithms (a TCU's self-diagnostic and reporting capability of malfunction data through CAN communication). Since all functions of TCU are implemented by embedded-software, it is hardly possible to analyze specifications by reverse engineering. In this paper a real-time transmission simulator adaptable to TCU is presented, for analysis of diagnosis algorithm and standards. Signal simulation circuits are deliberately designed considering electrical characteristics of TCU inputs and various analysis tools, such as analog input auto scan function, and global output enable switch, are implemented in software. Test results from hardware-in-the-loop simulator verify tolerance time for each error, as well as cause of fault, error reset conditions.

• Journal of Power Electronics
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• v.19 no.4
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• pp.1000-1010
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• 2019

The use of internal-model-based linear controller, such as resonant controller, is a well-established technique for the current control of grid-connected systems. Attractive properties for resonant controllers include their two-sequence tracking ability, the simple control structure, and the reduced computational burden. However, in the case of continuous-designed resonant controller, the transient performance is inevitably degraded at a low switching frequency. Moreover, available design methods for resonant controller is not able to realize the direct design of transient performances, and the anticipated transient performance is mainly achieved through trial and error. To address these problems, the zero-order-hold (ZOH) characteristic and inherent time delay in digital control systems are considered comprehensively in the design, and a corresponding hold-equivalent discrete model of the grid-connected converter is then established. The relationship between the placement of closed-loop poles and the corresponding transient performance is comprehensively investigated to realize the direct mapping relationship between the control gain and the transient response time. For the benefit of automatic tuning and real-time adaption, analytical expressions for controller gains are derived in detail using the required transient response time and system parameters. Simulation and experimental results demonstrate the validity of the proposed method.

• International Journal of Naval Architecture and Ocean Engineering
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• v.13 no.1
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• pp.617-627
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• 2021

Underwater Acoustic Channels (UAC) have inherent sparse characteristics. The traditional adaptive equalization techniques do not utilize this feature to improve the performance. In this paper we consider the Variable Adaptive Subgradient Projection (V-ASPM) method to derive a new sparse equalization algorithm based on the Minimum Symbol Error Rate (MSER) criterion. Compared with the original MSER algorithm, our proposed scheme adds sparse matrix to the iterative formula, which can assign independent step-sizes to the equalizer taps. How to obtain such proper sparse matrix is also analyzed. On this basis, the selection scheme of the sparse matrix is obtained by combining the variable step-sizes and equalizer sparsity measure. We call the new algorithm Sparse-Control Proportional-MSER (SC-PMSER) equalizer. Finally, the proposed SC-PMSER equalizer is embedded into a turbo receiver, which perform turbo decoding, Digital Phase-Locked Loop (DPLL), time-reversal receiving and multi-reception diversity. Simulation and real-field experimental results show that the proposed algorithm has better performance in convergence speed and Bit Error Rate (BER).

• Progress in Superconductivity and Cryogenics
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• v.11 no.3
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• pp.35-39
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• 2009

The study for a protective relay system is one of the important technical issues on the power system application of Superconducting Fault Current Limiter (SFCL). We used Real Time Digital Simulator(RTDS) to study the true interaction of the protection system with the power system. RTDS modeling of SFCL is necessary to the detailed protective relay tests. In this paper, we developed an analysis model using RTDS for studying the transient behavior of 22.9kV SFCL and carried out closed-loop testing of protective relays in distribution power system with the developed SFCL model. The SFCL model has the operation mechanism of 22.9kV hybrid SFCL being developed by LSIS and KEPRI in Korea. The parameters of the model are based on the test data of the real SFCL. Power system planners and operators can solve the expected problems in power system application of SFCL using protective relay testing results.