• 제목/요약/키워드: Digital front-end

검색결과 123건 처리시간 0.031초

온라인 디지털 컨텐츠 쇼핑몰의 MVC 기반 구현 (MVC Implementation of Online Digital Contents Shopping Mall)

  • 서주완;최민
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2015년도 춘계학술발표대회
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    • pp.1008-1011
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    • 2015
  • 본 연구는 디지털 컨텐츠를 판매하는 쇼핑몰에서 각 컨텐츠에 대해서 개별적으로 신용카드 기반으로 결제/판매할 수 있도록 하는 시스템이다. 이를 위해 본 연구에서는 PHP 기반 쇼핑몰 전반부(front-end)와 Spring MVC 기반 쇼핑몰 후반후(Back-end)를 분리하여 구현하였다. 전반부에서는 기본적으로 판매되는 각 디지털 컨텐츠를 분류별로 보여주는 기능을 구현하였고, 후반부에서는 각 디지털 컨텐츠에 대한 상세정보를 보여주며 신용카드 결제/IP 기반 접속제한/로깅(logging) 기능 등을 제공하도록 하였다. 특정 디지털 컨텐츠를 온라인으로 결제시에는 그로부터 24시간내에는 몇 번이고 다운로드 할 수 있도록 서비스 하기 위해서, E-rnail을 통한 인증코드(access code)를 제공하는 기능도 구현하였다. 또한, 이러한 구현을 Spring MVC 3.0 기반 구조에 의거하여 구현함으로써, 향후 시스템 유지보수성을 획기적으로 향상시켰다.

New Configuration of a PLDRO with an Interconnected Dual PLL Structure for K-Band Application

  • Jeon, Yuseok;Bang, Sungil
    • Journal of electromagnetic engineering and science
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    • 제17권3호
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    • pp.138-146
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    • 2017
  • A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

3V 저전력 CMOS 아날로그-디지털 변환기 설계 (Design of 3V a Low-Power CMOS Analog-to-Digital Converter)

  • 조성익;최경진;신홍규
    • 전자공학회논문지C
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    • 제36C권11호
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    • pp.10-17
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    • 1999
  • 본 논문에서는 MOS 트랜지스터로만 이루어진 CMOS IADC(Current-mode Analog-to-Digital Converter)를 설계하였다. 각 단은 CSH(Current Sample-and-Hold)와 CCMP(Current Comparator)로 구성된 1.5-비트 비트 셀로 구성되었다. 비트 셀 전단은 CFT(Clock Feedthrough)가 제거된 9-비트 해상도의 차동 CSH를 배치하였고, 각 단 비트 셀의 ADSC(Analog-to-Digital Subconverter)는 2개의 래치 CCMP로 구성되었다. 제안된 IADC를 현대 0.65 ㎛ CMOS 파라미터로 ACAD 시뮬레이션 한 결과, 20 Ms/s에서 100 ㎑의 입력 신호에 대한 SINAD(Signal to Noise-Plus-Distortion)은 47 ㏈ SNR (Signal-to-Noise)는 50 ㏈(8-bit)을 얻었고 35.7 ㎽ 소비전력 특성을 나타냈다.

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다기능 산소전극에 의한 산소투과특성 동시측정 (Simultaneous measurement of oxygen permeability by using of multi-functional oxygen electrode)

  • 이동희;정진휘;유형풍;김태진
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2000년도 하계학술대회 논문집
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    • pp.532-535
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    • 2000
  • We have fabricated a sensor system for on-line monitoring the oxygen permeability and diffusivity of six different polymer films using the miniaturized 6 cathode(Ag)-single anode(Ag/AgCl) type hexagonal oxygen electrode. This system consists of multiple input front-end electronics, signal conditioning circuit using the embedded microcontroller 80C196KC, PC interface circuit and PC with the OS for microcontroller and the operating program for this system. The digital low-[ass filter was programmed and the simulated filter characteristics were enough to eliminate the noise from sensor signal. According to the experimental results, the linearity coefficients of the output voltage to oxygen partial pressure for each sensor electrode of six cathode type oxygen sensor are 0.998, 0.997, 0.998, 0.997, 0.997, 0.997 respectively, and the response times are all within 4 minutes.

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MICRO INJECTOR BASED ON DIGITAL DRIVE AND CONTROL FOR BIOMEDICAL ENGINEERING

  • Hou, Liya;Zhang, Weiyi;Mu, Lili;Zhu, Li
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2003년도 ICCAS
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    • pp.2349-2351
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    • 2003
  • This paper reports a novel microfluidic system, by which microfluidic delivery, transport and control can be digitally realized in femtoliter scale. Microelectronic grade $N_2$ from a pressurized canister was passed through HPLC tubing into a micro injector. The micro injector was driven and controlled digitally by the control system that can apply various control parameters such as pulse frequencies. A front-end of micro nozzle was inserted the dyed oil to collect droplets injected. The diameter of a droplet was measured by a microscope and a CCD camera, and then its volume can be calculated on the assumption that the droplet is spherical. The micro nozzles were simply pulled in glass capillary tubes by the micro puller self-made, and the geometry parameters of the micro nozzles can be adjusted easily. Experiments have successfully been carried out, and the results demonstrated that the proposed digital micro injector possesses three significant advantages : precise ultra-small liquid volume in femtoliter scale, digital microfluidic control and micro devices fabricated by simple glass process, not based on IC process.

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2차 델타 시그마 변조기법을 이용한 고 정밀 및 고 안정 디지털 전자석 전원 장치에 관한 연구 (A Study on High Precision and High Stability Digital Magnet Power Supply Using Second Order Delta-Sigma modulation)

  • 김금수;장길진;김동희
    • 조명전기설비학회논문지
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    • 제29권3호
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    • pp.69-80
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    • 2015
  • This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

디지털자료실지원센터(DLS)의 이용자 집단간 만족도에 관한 연구 (A Study on the Satisfaction of User Groups of the Digital Library System)

  • 이병기
    • 정보관리학회지
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    • 제22권3호
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    • pp.129-145
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    • 2005
  • DLS(Digital Library System)는 학교도서관 관리자(사서교사)와 최종 이용자(일반교사 및 학생)에게 애플리케이션 서비스를 제공하기 위해서 교육인적자원부에서 개발한 학교도서관 정보시스템이다. DLS는 현재 15개 시 도교육청에 설치되어 있으며, 시 도교육청 관내의 초 중등학교에 서비스를 제공하고 있다. DLS는 서비스를 개시한지 2년 이상이 지났기 때문에 이용 실태와 현황을 분석하여 향후 개선 방안을 모색할 필요가 있다. 본 연구에서는 DLS를 사용하고 있는 전국의 308개 초 중등학교의 학교도서관 관리자, 학생 및 교사를 대상으로 이용실태와 요구사항을 조사하여 향후 개선 방안을 제시하고자 한다.

On-chip Inductor Modeling in Digital CMOS technology and Dual Band RF Receiver Design using Modeled Inductor

  • Han Dong Ok;Choi Seung Chul;Lim Ji Hoon;Choo Sung Joong;Shin Sang Chul;Lee Jun Jae;Shim SunIl;Park Jung Ho
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 학술대회지
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    • pp.796-800
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    • 2004
  • The main research on this paper is to model on-chip inductor in digital CMOS technology by using the foundry parameters and the physical structure. The s-parameters of a spiral inductor are extracted from the modeled equivalent circuit and then compared to the results obtained from HFSS. The structure and material of the inductor used for modeling in this work is identical with those of the inductor fabricated by CMOS process. To show why the modeled inductor instead of ideal inductor should be used to design a RF system, we designed dual band RF front-end receiver and then compared the results between when using the ideal inductor and using the modeled inductor.

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A 1.5 Gbps Transceiver Chipset in 0.13-μm CMOS for Serial Digital Interface

  • Lee, Kyungmin;Kim, Seung-Hoon;Park, Sung Min
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권4호
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    • pp.552-560
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    • 2017
  • This paper presents a transceiver chipset realized in a $0.13-{\mu}m$ CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of $1.485mm^2$, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of $1.44mm^2$.

Transceiver for Human Body Communication Using Frequency Selective Digital Transmission

  • Hyoung, Chang-Hee;Kang, Sung-Weon;Park, Seong-Ook;Kim, Youn-Tae
    • ETRI Journal
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    • 제34권2호
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    • pp.216-225
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    • 2012
  • This paper presents a transceiver module for human body communications whereby a spread signal with a group of 64 Walsh codes is directly transferred through a human body at a chip rate of 32 Mcps. Frequency selective digital transmission moves the signal spectrum over 5 MHz without continuous frequency modulation and increases the immunity to induced interference by the processing gain. A simple receiver structure with no additional analog circuitry for the transmitter has been developed and has a sensitivity of 250 ${\mu}V_{pp}$. The high sensitivity of the receiver makes it possible to communicate between mobile devices using a human body as the transmission medium. It enables half-duplex communication of 2 Mbps within an operating range of up to 170 cm between the ultra-mobile PCs held between fingertips of each hand with a packet error rate of lower than $10^{-6}$. The transceiver module consumes 59 mA with a 3.3 V power supply.