JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 1.5 Gbps Transceiver Chipset in 0.13-μm CMOS for Serial Digital Interface

  • Lee, Kyungmin (Department of Electronic and Electrical Engineering, Ewha Womans University) ;
  • Kim, Seung-Hoon (Department of Electronic and Electrical Engineering, Ewha Womans University) ;
  • Park, Sung Min (Department of Electronic and Electrical Engineering, Ewha Womans University)
  • Received : 2017.04.26
  • Accepted : 2017.07.11
  • Published : 2017.08.30
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Abstract

This paper presents a transceiver chipset realized in a $0.13-{\mu}m$ CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of $1.485mm^2$, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of $1.44mm^2$.

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References

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