• Journal of Broadcast Engineering
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• v.11 no.4 s.33
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• pp.521-532
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• 2006

Recently, many research initiatives have been underway to improve reception performance of ATSC based DTV signal in mobile channel by adopting multiple antennas. In this paper, we propose a new mobile channel model which can be applicable to any array geometry. And then we propose new channel estimation algorithm which uses PN5l1 sequence in field synch. The proposed algorithm is to estimate channel by correlating the input signal in If frequency band and finding maximum peak, which does not need complicated synchronization circuit. Finally, we propose new receiver structures which can be implemented at the front-end of the existing receiver with no modification. With computer simulation, we verify the performance of the proposed model and verify the performance of the receiver structure with computer simulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.6
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• pp.749-756
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• 2015

In this paper, we propose a unique systolic structure and communication algorithm that maintains a solid link between nodes using synchronous digital communication and enables low power communication. This system was designed by using CC2500 RF transceiver, CC2590 RF front end and C8051F330 low power microcontroller. The measurement of power consumption in the network link shows below $400{\mu}W$ in data transfer rate 320bps. The system constitutes the base unit of low power wireless network that was composed of each seven link nodes having eight sensor nodes. Results of the experiments show that link nodes using a 4Ah battery could operate over 3 years without replacement.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.672-678
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• 2017

In this paper, we studied a design method for a broadband quasi-Yagi antenna (QYA) for terrestrial digital television (DTV) reception. The proposed antenna is composed of a dipole driver, a rectangular patch type director close to the dipole, and a ground reflector printed on an FR4 substrate. A balun between a microstrip line and a coplanar strip (CPS) line is a rectangular patch inserted along the center of the CPS. The end of the balun is connected to the CPS line through a shorting pin. An antenna, as an design example for the proposed antenna, is designed for the operation in the frequency band of 470-806 MHz for terrestrial DTV, and the characteristics of the designed antenna are examined. The antenna has a good performance such as a frequency band of 430-842 MHz for a voltage standing wave ratio < 2, a gain > 3.7 dBi, and a front-to-back ratio > 7.4 dB.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.186-195
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• 1999

In this paper, the RF-modules composed of front-end, frequency synthesizer, modulator/demodulator and power control multi channel WLL personal system for W-CDMA using 10 [MHz] RF channel bandwidth has been implemented and considered. The measured transmission power is 250 [mW] which is very close to the required value. The measured flatness of power at the final output stage is ${\pm}1.5[dB]$ over the required bandwidth of the receiver. In addition, it is found that the chip rate transmitting spread signal is set to 8.192 [MHz], the required rate. The frequencies of RF_LO signal and LO signal of the modulator and the demodulator measured by a frequency synthesizer are satisfied with design requirements. The operating range of the receiving strength signal indicator and AGC units shows 60 [dB] respectively. Also the measured phasor diagram and eye pattern for deciding the RF modules compatible with baseband digital signal processing part are shown good results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.906-912
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• 2017

In this paper, we studied a design method for a broadband 3-element quasi-Yagi antenna (QYA) for indoor digital television (DTV) reception. The proposed QYA employs a novel balun between a microstrip (MS) line and a coplanar strip (CPS) line feeding the driver dipole. The proposed balun is constructed by connecting the end of MS line to CPS line through a shorting pin, and the CPS and ground reflector are connected through a circular ring-type conductor. An antenna, as an design example for the proposed antenna, is designed for the operation in the frequency band of 470-806 MHz for terrestrial DTV. The antenna fabricated on an FR4 substrate with a size of $270mm{\times}150mm$ showed a good performance such as a frequency band of 470-820 MHz for a voltage standing wave ratio < 2, a gain > 4.0 dBi, and a front-to-back ratio > 8.4 dB over the DTV frequency band.

• Journal of the Korea Society of Computer and Information
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• v.23 no.11
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• pp.111-122
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• 2018

The purpose of this study was to investigate the bodice prototype method suitable for the upper body shape of old-old aged women using the 3D anthropometric data. And it was to provide the basic data for the upper body garments of old-old aged women. In the overall appearance evaluation, the B pattern was rated as 4.00, and it was evaluated as the most suitable for the bodice prototype of the old-old aged woman. The E pattern was rated lower than normal, and the L pattern and the S pattern were found to be inadequate for older female bodice prototypes. As a result of the measurement of the waist and bust air gap of bodice prototype, the air gap of the bust was not significantly different between the patterns. But the waist air gap showed the largest difference between the L pattern and the S pattern. As a result of evaluating the appearance, the amount of space in the state of 3D simulation, and the air gap, the pattern B appeared to be the most appropriate prototype for the old-old aged women's body shape. However, there is a tendency that the shoulder end point is biased toward the back, so it is necessary to set the inclination of the back shoulder line to be more gentle. Conversely, the front shoulder should be more inclined. In the case of the 3D simulation, the B pattern showed that the other parts generally fit well. In the case of the 3D simulation program used in this study, it was evaluated that it is suitable only for the normal body shape because it is impossible to set the isometric angle which is one of the characteristics of the older female body shape. A study on the bodice prototype suitable for the bent body shape should be carried out through experiments on the actual body shape of various elderly women. In order to cope with the increase of elderly people who are familiar with digital, I think it is necessary to develop an avatar that reflects the old female body shape.

• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.58-62
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• 2010

This paper presents the effects of RF performance parameters on the Galileo receiver design via simulation after reviewing the requirements of the Galileo receiver structure. At first, we considered the general requirements, structure and characteristics of the Galileo system. Then we designed the Galileo receiver focused on performance requirement of 16 dB C/N which is equal to 15 % Error Vector Magnitude(EVM) by using Advanced Design System(ADS) simulation program. In order to verify the function of Automatic Gain Control(AGC)), we measured the IF output power level by changing the input power level at the front - end of the receiver. We analyzed the performance degradation due to phase noise variations of Local Oscillator(LO) in the Galileo receiver through EVM when the minimum sensitivity level of -127 dBm is applied at the receiver. We also analyzed the performance degradation according to variable Analog-to-Digital Converter(ADC) bits within the Dynamic range, -92 ~ -139 dBm, which has been defined by gain range (-2.5 ~ +42.5 dB) in the AGC operation. The results clearly show that the performance of the Galileo receiver can be improved by increasing ADC bits and reducing Phase Noise of LO.

• Information Systems Review
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• v.21 no.4
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• pp.143-156
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• 2019

Types of innovation can be categorized into simplification, information, automation, and intelligence. Intelligence is the highest level of innovation, and RPA can be seen as one of intelligence. Robotic Process Automation(RPA), a software robot with artificial intelligence, is an example of intelligence that is suited for simple, repetitive, large-scale transaction processing tasks. The RPA, which is already in operation in many companies in Korea, shows what needs to be done to naturally focus on the core tasks in a situation where the need for a strong organizational culture is increasing and the emphasis is on voluntary leadership, strong teamwork and execution, and a professional working culture. The introduction was considered naturally according to the need to find. Robotic Process Automation, or RPA, is a technology that replaces human tasks with the goal of quickly and efficiently handling structural tasks. RPA is implemented through software robots that mimic humans using software such as ERP systems or productivity tools. RPA robots are software installed on a computer and are called robots by the principle of operation. RPA is integrated throughout the IT system through the front end, unlike traditional software that communicates with other IT systems through the back end. In practice, this means that software robots use IT systems in the same way as humans, repeat the correct steps, and respond to events on the computer screen instead of communicating with the system's application programming interface(API). Designing software that mimics humans to communicate with other software can be less intuitive, but there are many advantages to this approach. First, you can integrate RPA with virtually any software you use, regardless of your openness to third-party applications. Many enterprise IT systems are proprietary because they do not have many common APIs, and their ability to communicate with other systems is severely limited, but RPA solves this problem. Second, RPA can be implemented in a very short time. Traditional software development methods, such as enterprise software integration, are relatively time consuming, but RPAs can be implemented in a relatively short period of two to four weeks. Third, automated processes through software robots can be easily modified by system users. While traditional approaches require advanced coding techniques to drastically modify how they work, RPA can be instructed by modifying relatively simple logical statements, or by modifying screen captures or graphical process charts of human-run processes. This makes RPA very versatile and flexible. This RPA is a good example of the application of digital to intelligence(D2I).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.