• Title/Summary/Keyword: Digital delay

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A High Speed and Low Jitter PLL Clock generator (고속 저잡음 PLL 클럭 발생기)

  • Cho, Jeong-Hwan;Chong, Jong-Wha
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.3
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    • pp.1-7
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    • 2002
  • This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

The Efficient Design Method Of ROM Accessed Address In Due Sequence (순차 주소 접근 ROM의 효율적인 설계 방법)

  • Kim, Yong-Eun;Kim, Kang-Jik;Cho, Seong-Ik;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.8
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    • pp.18-21
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    • 2009
  • In the digital system, ROM has a large power-consumption and a speed-bottleneck. According to gradual growth of system speed, ROM is demanded to have low-power consumption and high-speed operation design. The ROM adapted in FFT or FIR filter needs method of sequential accessed addressing. We proposed a reduction method for the number of storage cells in this paper. The number of storage cells which is connected with bi-line is reduced by the proposed method so that the capacitance value of bit-time is reduced. In this case, delay time, and power consumption are reduced. Design result of ROM in this paper using the proposed method could reduce up to 86.3% of storage cell '1' compare with conventional method.

A Study on the Nail Discoloration of the Polish (폴리쉬 사용으로 인한 네일 변색에 관한 연구)

  • Lee, Young-Suk;Park, Young-Seon
    • The Research Journal of the Costume Culture
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    • v.19 no.2
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    • pp.309-315
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    • 2011
  • Due to rapid growth of nail art industry, various materials and expression tools are have been developed. Increasing number of consumers favor diverse nail art techniques including painting and artificial tips in addition to basic care such as cuticle trimming or coloring. Accordingly, the diversity of polish colors has been settled as a concept of total fashion in addition to the clothes and accessories. As the result, nails may be damaged or discolored. A study the nail discoloration by using polish was purposed that contribute to the development of nail protective products. The tests were conducted with 20 college students for six months from March 3 to Aug. 28, 2009, using digital camera as the measurement apparatus. The students were classified into two groups which applied bright polish (white, beige, pink series) and dark polish (purple, blue, black series), and then divided into the groups applied and not applied the base coat which is known to be effective in preventing nail discoloration, and the groups applied and not applied tonic. The students applied polish for one week, and removed the polish with remover and photographed to examine the degree of nail discoloration. Dark colored polished resulted in earlier coloration and discoloration than the bright colored ones. Base coat could prevent coloration and the color changes of hyponychium and eponychium were lighter than the cases not applied with base coat. Tonic could delay coloration and reduced the color changes of hyponychium showing that tonic was effective for preventing coloration and discoloration of nail in addition to nutrition.

Algorithm of Converged Corner Detection-based Segmentation in the Data Matrix Barcode (코너 검출 기반의 융합형 Data Matrix 바코드 분할 알고리즘)

  • Han, Hee-June;Lee, Jong-Yun
    • Journal of the Korea Convergence Society
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    • v.6 no.1
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    • pp.7-16
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    • 2015
  • A segmentation process extracts an interesting area of barcode in an image and gives a crucial impart on the performance of barcode verifier. Previous segmentation methods occurs some issues as follows. First, it is very hard to determine a threshold of length in Hough Line transform because it is sensitive. Second, Morphology transform delays the process when you conduct dilation and erosion operations during the image extraction. Therefore, we proposes a novel Converged Harris Corner detection-based segmentation method to detect an interesting area of barcode in Data Matrix. In order to evaluate the performance of proposed method, we conduct experiments by a dataset of barcode in accordance with size and location in an image. In result, our method solves the problems of delay and surrounding environments, threshold setting, and extracts the barcode area 100% from test images.

Implementation and Design of Wideband IFIU using Aperture Open Loop Resonator and Reversed Phase Technique (역 위상 기법과 Aperture를 갖는 개방형 루프 공진기를 사용한 광대역 IF 모듈 설계 및 제작)

  • 김영완
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.11
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    • pp.17-23
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    • 2004
  • The implementation and design of the wideband IFIU using aperture open loop resonator and reversed phase technique to reduce the local oscillator leakage signal was represented in this paper. The local oscillator leakage signal is generated in stage of frequency conversion, especially in frequency conversion of fully digital modulation signal close to DC signal. The leakage signal and spurious signals, which have effects on adjacent channel or in-band channel as interference signals, were reduced below -60 dBc for 45 Mbps and 155 Mbps IF interface units. The group delay for both IFIUs shows low ripple characteristics of 15 ns and 8 ns, respectively. Also, the amplitude ripple characteristic in 150 MHz bandwidth with L-band center frequency satisfies the required specification of 2 dB. The implemented IFIU provides the required specifications for wideband satellite communication system.

Performance of PPSM System in multipath channel for UWB Communication (다중경로 환경을 고려한 PPSM 임펄스 시스템의 성능 분석)

  • Park Ho-Hwan;Kim Jin-Su;Hwang Hyeon-Chyeol;Kwak Kyung-Sup
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.2 s.344
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    • pp.7-15
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    • 2006
  • Recently, Ultra-wideband (UWB) Communication systems have become a popular research topic. UWB system is characterized by the fact that the digital information represented by a subnanosecond pulses is transmitted through the air. In this paper, we consider the PPSM scheme that combine PPM and PSM. We provide the performance in AWGN and SV multipath channel which consists of $CM1\~CM4$. The optimal symbol set for M-ary system in multipath channel which shows good performance is also presented. The simulation results show that the performance in CM4 is worse than that in CMI due to long delay spread, many multipath components, 4-ary system outperforms binary system in Low$E_b/N_0$ but not in high $E_b/N_0$. We find system have the optimal symbol set in multipath channel.

Robust Double Deadbeat Control of Single-Phase UPS Inverter (단상 UPS 인버터의 강인한 2중 데드비트제어)

  • 박지호;허태원;안인모;이현우;정재륜;우정인
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.15 no.6
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    • pp.65-72
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    • 2001
  • This paper deals with a novel full digital control of the single-phase PWM(Pulse Width Modulation) inviter for UPS(Uninterruptible Power Supp1y). The voltage and current of output filter capacitor as a state variable are the feedback control input. In the proposed scheme a double deadbeat control consisting of minor current control loop and major voltage control loop have been developed In addition, a second order deadbeat currents control which should be exactly equal to its reference in two sampling time without error and overshoot is proposed to remove the influence of the calculation time delay. The load current prediction is achieved to compensate the load disturbance. The simulation and experimental result shows that the proposed system offers an output voltage with THD(Total Harmonic Distortion) less than 5% at a full nonlinear load.

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Dead Time Compensation and Polarity Check of Phase Currents Based on Programmable Low-pass Filter for Automotive Electric Drive Systems (자동차 전동 시스템을 위한 Programmable 저역 통과 필터 기반의 상전류 극성 판단 및 데드타임 보상)

  • Choi, Chinchul;Lee, Kangseok;Lee, Wootaik
    • Transactions of the Korean Society of Automotive Engineers
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    • v.22 no.6
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    • pp.23-30
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    • 2014
  • This paper proposes a dead time compensation method for an AC motor drive using phase current polarity information which is detected based on a digital programmable low-pass filter (PLPF). The polarity detection using the PLPF is an alternative solution of a conventional method which uses a general low-pass filter (LPF) and hysteresis bands in order to avoid jittering due to noises. The PLPF not only adjusts its cutoff frequency according to the synchronous frequency of AC motors but also eliminates a gain attenuation and phase delay which are main problems of the general LPF. Through the PLPF, a fundamental component signal without gain and phase distortions is extracted from the measured raw current signal with noise. By use of the fundamental component, the polarity of current is effectively detected by reducing the hysteresis band. Finally, the proposed method compensates the dead time effects by adding or subtracting average voltage value to voltage references of the controller according to the detected current polarity information. The proposed compensation method is experimentally verified by compared with the conventional method.

Estimation for application of the Runoff Analysis using TOPMODEL at an ungaged watershed (미계측유역에 대한 TOPMODEL의 적용성 평가)

  • Kang, Sung-Jun;Park, Young-Gi
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.3
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    • pp.1458-1464
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    • 2011
  • This study is on the application of TOPMODEL-topographic based hydrologic model-to the runoff analysis, The test area was the ssang-chi watershed which is mountainous catchment located in the upstream of the sumjin-gang basin and the watershed area is $126.7km^2$. The six's hourly runoff and precipitation data was selected in the 2006 ~ 2009 year. And the model parameters are calibrated using observed runoff data by Pattern Search method. The topographic index of the ssang-chi catchment was produced by digital elevation model(DEM) of 100m grid. As a results of the analysis, the parameters of model, a decay facter(m), transmissivity(T0), and the unsaturated zone delay(TD) are sensible to hydrologic response, and the simulated runoff data are in good agreement with observed runoff data.

Electrical Characteristic of Power MOSFET with Zener Diode for Battery Protection IC

  • Kim, Ju-Yeon;Park, Seung-Uk;Kim, Nam-Soo;Park, Jung-Woong;Lee, Kie-Yong;Lee, Hyung-Gyoo
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.1
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    • pp.47-51
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    • 2013
  • A high power MOSFET switch based on a 0.35 ${\mu}m$ CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 ${\mu}m$-thick epi-taxy layer is integrated with a Zener diode. The p-n+Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been developed for a rechargeable battery. The experiment indicates that both breakdown voltage and leakage current depend on the doping concentration of the Zener diode. The dependency of the breakdown voltage on doping concentration is in a trade-off relationship with that of the leakage current. The breakdown voltage is obtained to exceed 14 V and the leakage current is controlled under 0.5 ${\mu}A$. The proposed integrated module with the application of the power MOSFET indicates the high performance of the protection IC, where the overcharge delay time and detection voltage are controlled within 1.1 s and 4.2 V, respectively.