• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• Journal of Power Electronics
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• v.11 no.2
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• pp.156-162
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• 2011

The control loop time delay caused by sampling, the zero-order-holder effect and calculations is inevitable in the digital control of dc-dc switching converters. The time delay will limit the bandwidth of the control loop and therefore degrade the transient performance of digital systems. In this paper, the quantization time delay effects with different time delay values based on a generic second-order system are analyzed. The conclusion that the bandwidth of digital control is reduced by about 20% with a one cycle delay and by 50% with two cycles of delay in comparison with no time delay is obtained. To compensate the time delay and to increase the control loop bandwidth, a duty ratio predictive control scheme based on linear extrapolation is proposed. The compensation effect and a comparison of the load variation transient response characteristics with analogy control, conventional digital control and duty ratio predictive control with different time delay values are performed on a point-of-load Buck converter by simulations and experiments. It is shown that, using the proposed technique, the control loop bandwidth can be increased by 50% for a one cycle delay and 48.2% for two cycles of delay when compared to conventional digital control. Simulations and experimental results prove the validity of the conclusion of the quantization effects of the time delay and the proposed control scheme.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.103-106
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• 2010

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

• Science of Emotion and Sensibility
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• v.11 no.2
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• pp.227-234
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• 2008

Graphic and sounds are mainly used for presenting digital content as general. It has been reported that the reality of digital contents was improved by adding haptic factor to the contents of graphic and sounds. Therefore, various haptic system have recently been developed for implementing haptic sensation into digital contents. However, the delay of haptic display sometimes happens due to low hardware performance and causes to deteriorate reality of digital contents. The delay effect on reality has been important to be determined for presenting digital contents with haptic system. Therefore, this study is to find the effect on user's cognition of digital contents evoking both visual and haptic sensation. Eight university students performed 4 repetitive tasks of pushing cube under the two conditions of visual and haptic delay. The delay time of each condition were set 0.5, 1.0, 2.0 and 4.0 second. As the result, both haptic and visual delay were negatively influenced user's recognition while visual delay showed more dominant effect on user's recognition than haptic delay.

• Journal of Power Electronics
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• v.12 no.1
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• pp.98-103
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• 2012

This paper presents a digital pulse width modulator (DPWM) with a reduced digital modulation delay (a transport delay of the modulator) during the transient response of power converters. During the transient response operation of a power converter, as a result of dynamic variations such as load step-up or step-down, the closed loop controller will continuously adjust the duty cycle in order to regulate the output voltage. The larger the modulation delays, the larger the undesired output voltage deviation from the reference point. The three conventional DPWM techniques exhibit significant leading-edge and/or trailing-edge modulation delays. The DPWM technique proposed in this paper, which results in modulation delay reductions, is discussed, experimentally tested and compared with conventional modulation techniques.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.5
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• pp.423-431
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• 2000

In this paper, the effect of computing time-delay in the real-time digital fuzzy control systems is investigated and the design methodology of a real-time digital fuzzy controller(DFC) to overcome the problems caused by it is presented. We propose the fuzzy feedback controller whose output is delayed with unit sampling period. The analysis and the design problem considering computing time-delay is very easy because the proposed controller is syncronized with the sampling time. The stabilization problem of the digital fuzzy control system is solved by the linear matrix inequality(LMI) theory. Convex optimization techniques are utilized to find the stable feedback gains and a common positive definite matrix P for the designed fuzzy control system Furthermore, we develop a real-time fuzzy control system for backing up a computer-simulated truck-trailer with the consideration of the computing time-delay. By using the proposed method, we design a DFC which guarantees the stability of the real time digital fuzzy control system in the presence of computing time-delay.

• The Journal of the Acoustical Society of Korea
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• v.22 no.8
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• pp.680-686
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• 2003

Digital waveguide model is a general method that is used in physical modeling of musical instruments. Wave motion is analyzed by time or by space in digital waveguide model. Because sampling is made via time, it is general that musical instrument model is described by wave motion of time. In this paper, we synthesized the musical instrument sound by adding instrument body model to the spatial based string model. In this way, we could improve sound quality and process musical instrument model's tone control variables effectively. We explained about delay error that happens in string and body in space based sampling and showed method to process fractional delay using FD (Fractional Delay)filter. Finally, we explained the relation between tone quality and number of delays. And we also compared the result with time base digital waveguide model.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.932-934
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• 2006

A relationship between discharge delay time and the aging method were investigated: A-Y (Address electrode - Scan electrode) aging and conventional X-Y(Common electrode - Scan electrode) aging with the variation of sustain voltage beyond self-erasing discharge. Although A-Y aging decreases discharge delay time, it has several drawbacks like non-uniformity of discharge, degradation of luminous efficiency and a color temperature. In a conventional aging condition which is carried out near the mid-margin voltage, discharge delay time is short in low voltage and high frequency condition. As an alternative to conventional voltage aging, high voltage aging is suggested which is carried out at self-erasing sustain voltage region. High voltage aging shows lower discharge delay time and fast aging speed than conventional voltage aging.